m5-dev@m5sim.org

4

replies

[gem5-dev] Change in gem5/gem5[master]: sim: Initialise data members

started 2018-10-01 13:44:13 UTC

2018-11-28 20:12:36 UTC

Giacomo Gabrielli (Gerrit)

2

replies

[gem5-dev] Change in gem5/gem5[master]: base, arch-arm: clang compilation fixes

started 2018-11-28 16:45:48 UTC

2018-11-28 17:45:55 UTC

Giacomo Travaglini (Gerrit)

2

replies

[gem5-dev] Change in gem5/gem5[master]: tests: Convert IniFile unit test to a GTest

started 2018-11-26 23:23:03 UTC

2018-11-28 15:54:18 UTC

Giacomo Travaglini (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: hsail: Fix a warning/build failure for HSAIL_X86.

started 2018-11-27 09:15:57 UTC

2018-11-28 04:02:51 UTC

Gabe Black (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: arch, base, cpu, gpu,

started 2018-11-27 07:55:31 UTC

2018-11-28 03:58:27 UTC

Gabe Black (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: base: IniFile dumping to ostream

started 2018-11-27 19:40:22 UTC

2018-11-27 19:40:22 UTC

Giacomo Travaglini (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: sim-se: only implement getdentsFunc on supported hosts

started 2018-11-24 00:03:07 UTC

2018-11-27 17:46:37 UTC

Ciro Santilli (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: systemc: set endianess to fix build for ARM host

started 2018-11-23 23:55:47 UTC

2018-11-27 17:46:24 UTC

Ciro Santilli (Gerrit)

4

replies

[gem5-dev] Change in gem5/gem5[master]: - Add new ARM platform VExpress_GEM5_V2 with GICv3. Support up to 256...

started 2018-11-05 22:32:11 UTC

2018-11-27 16:47:11 UTC

Jairo Balart (Gerrit)

3

replies

[gem5-dev] Change in gem5/gem5[master]: cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

started 2018-10-19 05:59:40 UTC

2018-11-27 09:12:23 UTC

Gabe Black (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: base: Add some functions to convert floats to bits and vice versa.

started 2018-11-20 09:30:54 UTC

2018-11-27 06:46:48 UTC

Gabe Black (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: cpu: Use correct way index in the LTAGE loop predictor

started 2018-11-27 04:02:14 UTC

2018-11-27 04:02:14 UTC

Louis Delhez (Gerrit)

0

replies

[gem5-dev] ARM SVE Patchset

started 2018-11-26 21:55:52 UTC

2018-11-26 21:55:52 UTC

Giacomo Travaglini

3

replies

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add setters to validate and secure block

started 2018-11-15 21:45:35 UTC

2018-11-26 18:49:20 UTC

Daniel Carvalho (Gerrit)

6

replies

[gem5-dev] Change in gem5/gem5[master]: mem-cache: virtual address support for prefetchers

started 2018-11-18 18:49:35 UTC

2018-11-26 17:34:09 UTC

Javier Bueno Hedo (Gerrit)

0

replies

[gem5-dev] Mail bounces

started 2018-11-25 21:49:08 UTC

2018-11-25 21:49:08 UTC

Daniel Carvalho

0

replies

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression --scratch all

started 2018-11-25 21:45:47 UTC

2018-11-25 21:45:47 UTC

Cron Daemon

0

replies

[gem5-dev] Change in gem5/gem5[master]: cpu: Added parameters to enable/disable features in LTAGE

started 2018-11-24 04:37:02 UTC

2018-11-24 04:37:02 UTC

Pau Cabre (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implementing multiple level TLB hierarchy and new table wal...

started 2018-11-08 23:17:38 UTC

2018-11-23 14:00:30 UTC

Ivan Pizarro (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Reverting some changes in the headers for tlb and table_wal...

started 2018-11-23 00:53:28 UTC

2018-11-23 00:53:28 UTC

Ivan Pizarro (Gerrit)

4

replies

[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers

started 2018-10-23 14:48:42 UTC

2018-11-22 23:38:04 UTC

Giacomo Gabrielli (Gerrit)

3

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for the Scalable Vector Extension

started 2018-10-15 21:09:31 UTC

2018-11-22 23:35:15 UTC

Giacomo Gabrielli (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Additional bits in misc ARM registers to use with the TLB a...

started 2018-11-22 22:32:13 UTC

2018-11-22 22:32:13 UTC

Ivan Pizarro (Gerrit)

1

reply

[gem5-dev] Change in gem5/gem5[master]: cpu: Made LTAGE parameters configurable

started 2018-11-19 05:37:08 UTC

2018-11-22 17:46:57 UTC

Pau Cabre (Gerrit)

3

replies

[gem5-dev] Change in gem5/gem5[master]: cpu: Fixes on the loop predictor part of LTAGE

started 2018-11-12 04:44:52 UTC

2018-11-22 17:46:57 UTC

Pau Cabre (Gerrit)

2

replies

[gem5-dev] Change in gem5/gem5[master]: cpu: Fixed useful counter handling in LTAGE

started 2018-11-11 04:37:17 UTC

2018-11-22 17:46:57 UTC

Pau Cabre (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: cpu, arch: Replace the CCReg type with RegVal.

started 2018-11-22 06:24:00 UTC

2018-11-22 06:24:00 UTC

Gabe Black (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: correctly set floats from GDB on aarch64

started 2018-11-22 00:08:52 UTC

2018-11-22 00:08:52 UTC

Ciro Santilli (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: fix the aarch64 GDB stub

started 2018-11-22 00:08:52 UTC

2018-11-22 00:08:52 UTC

Ciro Santilli (Gerrit)

0

replies

[gem5-dev] Change in gem5/gem5[master]: arch-arm: only change the pc address when GDB registers are set

started 2018-11-22 00:08:52 UTC

2018-11-22 00:08:52 UTC

Ciro Santilli (Gerrit)