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[gem5-dev] Change in gem5/gem5[master]: arch, cpu: Add vector predicate registers
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Giacomo Gabrielli (Gerrit)
2018-10-23 09:48:42 UTC
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Giacomo Gabrielli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13715


Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/pred_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
50 files changed, 1,320 insertions(+), 70 deletions(-)



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 5ea7a6a..e1295b1 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -1,6 +1,6 @@
# -*- mode:python -*-

-# Copyright (c) 2016 ARM Limited
+# Copyright (c) 2016-2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -226,6 +226,8 @@
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
DebugFlag('VecRegs')
+DebugFlag('PredRegs')
DebugFlag('CCRegs')
DebugFlag('MiscRegs')
-CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'PredRegs',
+ 'CCRegs', 'MiscRegs' ])
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36e7084..d82512a 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -122,6 +122,12 @@
return reg;
}

+ int
+ flattenPredIndex(int reg) const
+ {
+ return reg;
+ }
+
// dummy
int
flattenCCIndex(int reg) const
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 53ade47..d760eb7 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -33,6 +33,7 @@

#include "arch/alpha/generated/max_inst_regs.hh"
#include "arch/alpha/ipr.hh"
+#include "arch/generic/pred_reg.hh"
#include "arch/generic/types.hh"
#include "arch/generic/vec_reg.hh"
#include "base/types.hh"
@@ -57,14 +58,22 @@
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

-// dummy typedefs since we don't have vector regs
+// dummy typedefs and constants since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// dummy typedefs and constants since we don't have predicate regs
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

enum MiscRegIndex
{
@@ -97,6 +106,8 @@

const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
+const int NumVecRegs = 1; // Not applicable to Alpha
+const int NumPredRegs = 1; // Not applicable to Alpha
const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 885190c..5a86b1a 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -434,6 +434,8 @@
return RegId(VecRegClass, flattenVecIndex(regId.index()));
case VecElemClass:
return RegId(VecElemClass,
flattenVecElemIndex(regId.index()));
+ case PredRegClass:
+ return RegId(PredRegClass,
flattenPredIndex(regId.index()));
case CCRegClass:
return RegId(CCRegClass, flattenCCIndex(regId.index()));
case MiscRegClass:
@@ -496,6 +498,13 @@
}

int
+ flattenPredIndex(int reg) const
+ {
+ assert(reg >= 0);
+ return reg;
+ }
+
+ int
flattenCCIndex(int reg) const
{
assert(reg >= 0);
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index e7defd1..1683452 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -47,6 +47,7 @@
#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
#include "arch/arm/miscregs.hh"
+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"

namespace ArmISA {
@@ -72,6 +73,17 @@
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;

+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// Dummy typedefs
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);
+
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;

@@ -91,12 +103,14 @@
const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
+const int NumPredRegs = 1;
const int NumCCRegs = NUM_CCREGS;
const int NumMiscRegs = NUM_MISCREGS;

#define ISA_HAS_CC_REGS

-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
NumMiscRegs;
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
NumPredRegs +
+ NumMiscRegs;

// semantically meaningful register indices
const int ReturnValueReg = 0;
diff --git a/src/arch/generic/pred_reg.hh b/src/arch/generic/pred_reg.hh
new file mode 100644
index 0000000..a67ba35
--- /dev/null
+++ b/src/arch/generic/pred_reg.hh
@@ -0,0 +1,387 @@
+// Copyright (c) 2017 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Giacomo Gabrielli
+// Rekai Gonzalez
+// Javier Setoain
+
+#ifndef __ARCH_GENERIC_PRED_REG_HH__
+#define __ARCH_GENERIC_PRED_REG_HH__
+
+#include <array>
+#include <cassert>
+#include <vector>
+
+#include "base/cprintf.hh"
+
+template <size_t NumBits, bool Packed>
+class PredRegContainer;
+
+/// Predicate register view.
+///
+/// This generic class implements the View in an MVC pattern, similarly to
+/// @see VecRegT. Since predicates are mainly used in conjunction with
vectors
+/// to specify which lanes are active in a vector operation, the class is
+/// templated on the vector element type to simplify ISA definitions.
+/// @tparam VecElem Type of the vector elements.
+/// @tparam NumElems Number of vector elements making up the view.
+/// @tparam Packed True if the predicate register relies on a packed
+/// representation, i.e. adjacent bits refer to different vector elements
+/// irrespective of the vector element size (e.g. this is the case for
+/// AVX-512). If false, the predicate register relies on an unpacked
+/// representation, where each bit refers to the corresponding byte in a
vector
+/// register (e.g. this is the case for ARM SVE).
+/// @tparam Const True if the underlying container can be modified through
+/// the view.
+template <typename VecElem, size_t NumElems, bool Packed, bool Const>
+class PredRegT
+{
+ protected:
+ /// Size of the register in bits.
+ static constexpr size_t NUM_BITS = Packed ? NumElems :
+ sizeof(VecElem) * NumElems;
+
+ public:
+ /// Container type alias.
+ using Container = typename std::conditional<
+ Const,
+ const PredRegContainer<NUM_BITS, Packed>,
+ PredRegContainer<NUM_BITS, Packed>>::type;
+
+ protected:
+ // Alias for this type
+ using MyClass = PredRegT<VecElem, NumElems, Packed, Const>;
+ /// Container corresponding to this view.
+ Container& container;
+
+ public:
+ PredRegT(Container& c) : container(c) {}
+
+ /// Reset the register to an all-false value.
+ template<bool Condition = !Const>
+ typename std::enable_if<Condition, void>::type
+ reset() { container.reset(); }
+
+ /// Reset the register to an all-true value.
+ template<bool Condition = !Const>
+ typename std::enable_if<Condition, void>::type
+ set() { container.set(); }
+
+ template<bool Condition = !Const>
+ typename std::enable_if<Condition, MyClass&>::type
+ operator=(const MyClass& that)
+ {
+ container = that.container;
+ return *this;
+ }
+
+ const bool&
+ operator[](size_t idx) const
+ {
+ return container[idx * (Packed ? 1 : sizeof(VecElem))];
+ }
+
+ template<bool Condition = !Const>
+ typename std::enable_if<Condition, bool&>::type
+ operator[](size_t idx)
+ {
+ return container[idx * (Packed ? 1 : sizeof(VecElem))];
+ }
+
+ /// Return an element of the predicate register as it appears
+ /// in the raw (untyped) internal representation
+ uint8_t
+ get_raw(size_t idx) const
+ {
+ return container.get_bits(idx * (Packed ? 1 : sizeof(VecElem)),
+ (Packed ? 1 : sizeof(VecElem)));
+ }
+
+ /// Write a raw value in an element of the predicate register
+ template<bool Condition = !Const>
+ typename std::enable_if<Condition, void>::type
+ set_raw(size_t idx, uint8_t val)
+ {
+ container.set_bits(idx * (Packed ? 1 : sizeof(VecElem)),
+ (Packed ? 1 : sizeof(VecElem)), val);
+ }
+
+ /// Equality operator, required to compare thread contexts.
+ template<typename VE2, size_t NE2, bool P2, bool C2>
+ bool
+ operator==(const PredRegT<VE2, NE2, P2, C2>& that) const
+ {
+ return container == that.container;
+ }
+
+ /// Inequality operator, required to compare thread contexts.
+ template<typename VE2, size_t NE2, bool P2, bool C2>
+ bool
+ operator!=(const PredRegT<VE2, NE2, P2, C2>& that) const
+ {
+ return !operator==(that);
+ }
+
+ friend std::ostream&
+ operator<<(std::ostream& os, const MyClass& p)
+ {
+ // 0-sized is not allowed
+ os << '[' << p.container[0];
+ for (int i = 0; i < p.NUM_BITS; ++i) {
+ os << " " << (p.container[i] ? 1 : 0);
+ }
+ os << ']';
+ return os;
+ }
+
+ /// Returns a string representation of the register content.
+ const std::string print() const { return csprintf("%s", *this); }
+
+ /// Returns true if the first active element of the register is true.
+ /// @param mask Input mask used to filter the predicates to be tested.
+ /// @param actual_num_elems Actual number of vector elements
considered for
+ /// the test (corresponding to the current vector length).
+ template <bool MC>
+ bool
+ firstActive(const PredRegT<VecElem, NumElems, Packed, MC>& mask,
+ size_t actual_num_elems) const
+ {
+ assert(actual_num_elems <= NumElems);
+ for (int i = 0; i < actual_num_elems; ++i) {
+ if (mask[i]) {
+ return (*this)[i];
+ }
+ }
+ return false;
+ }
+
+ /// Returns true if there are no active elements in the register.
+ /// @param mask Input mask used to filter the predicates to be tested.
+ /// @param actual_num_elems Actual number of vector elements
considered for
+ /// the test (corresponding to the current vector length).
+ template <bool MC>
+ bool
+ noneActive(const PredRegT<VecElem, NumElems, Packed, MC>& mask,
+ size_t actual_num_elems) const
+ {
+ assert(actual_num_elems <= NumElems);
+ for (int i = 0; i < actual_num_elems; ++i) {
+ if (mask[i] && operator[](i)) {
+ return false;
+ }
+ }
+ return true;
+ }
+
+ /// Returns true if the last active element of the register is true.
+ /// @param mask Input mask used to filter the predicates to be tested.
+ /// @param actual_num_elems Actual number of vector elements
considered for
+ /// the test (corresponding to the current vector length).
+ template <bool MC>
+ bool
+ lastActive(const PredRegT<VecElem, NumElems, Packed, MC>& mask,
+ size_t actual_num_elems) const
+ {
+ assert(actual_num_elems <= NumElems);
+ for (int i = actual_num_elems - 1; i >= 0; --i) {
+ if (mask[i]) {
+ return operator[](i);
+ }
+ }
+ return false;
+ }
+};
+
+/// Generic predicate register container.
+///
+/// This generic class implements the Model in an MVC pattern, similarly to
+/// @see VecRegContainer.
+/// @tparam NumBits Size of the container in bits.
+/// @tparam Packed See @VecRegT.
+template <size_t NumBits, bool Packed>
+class PredRegContainer
+{
+ static_assert(NumBits > 0,
+ "Size of a predicate register must be > 0");
+
+ public:
+ static constexpr size_t NUM_BITS = NumBits;
+ using Container = std::array<bool, NumBits>;
+
+ private:
+ Container container;
+ // Alias for this type
+ using MyClass = PredRegContainer<NumBits, Packed>;
+
+ public:
+ PredRegContainer() {}
+
+ MyClass&
+ operator=(const MyClass& that)
+ {
+ if (&that == this)
+ return *this;
+ container = that.container;
+ return *this;
+ }
+
+ /// Required for de-serialization.
+ MyClass&
+ operator=(const std::vector<uint8_t>& that)
+ {
+ assert(that.size() == NUM_BITS);
+ std::copy(that.begin(), that.end(), container.begin());
+ return *this;
+ }
+
+ /// Resets the predicate register to an all-false register.
+ void
+ reset()
+ {
+ container.fill(false);
+ }
+
+ /// Sets the predicate register to an all-true value.
+ void
+ set()
+ {
+ container.fill(true);
+ }
+
+ /// Equality operator, required to compare thread contexts.
+ template<size_t N2, bool P2>
+ inline bool
+ operator==(const PredRegContainer<N2, P2>& that) const
+ {
+ return NumBits == N2 && Packed == P2 && container ==
that.container;
+ }
+
+ /// Inequality operator, required to compare thread contexts.
+ template<size_t N2, bool P2>
+ bool
+ operator!=(const PredRegContainer<N2, P2>& that) const
+ {
+ return !operator==(that);
+ }
+
+ /// Returns a reference to a specific element of the internal
container.
+ bool& operator[](size_t idx) { return container[idx]; }
+
+ /// Returns a const reference to a specific element of the internal
+ /// container.
+ const bool& operator[](size_t idx) const { return container[idx]; }
+
+ /// Returns a subset of bits starting from a specific element in the
+ /// container.
+ uint8_t get_bits(size_t idx, uint8_t nbits) const
+ {
+ assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
+ uint8_t v = 0;
+ idx = idx + nbits - 1;
+ for (int i = 0; i < nbits; ++i, --idx) {
+ v <<= 1;
+ v |= container[idx];
+ }
+ return v;
+ }
+
+ /// Set a subset of bits starting from a specific element in the
+ /// container.
+ void set_bits(size_t idx, uint8_t nbits, uint8_t bval)
+ {
+ assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
+ for (int i = 0; i < nbits; ++i, ++idx) {
+ container[idx] = bval & 1;
+ bval >>= 1;
+ }
+ }
+
+ /// Returns a string representation of the register content.
+ const std::string print() const { return csprintf("%s", *this); }
+
+ friend std::ostream& operator<<(std::ostream& os, const MyClass& v)
+ {
+ for (auto b: v.container) {
+ os << csprintf("%d", b);
+ }
+ return os;
+ }
+
+ /// Create a view of this container.
+ ///
+ /// If NumElems is provided, the size of the container is
bounds-checked,
+ /// otherwise the size is inferred from the container size.
+ /// @tparam VecElem Type of the vector elements.
+ /// @tparam NumElems Number of vector elements making up the view.
+ /// @{
+ template <typename VecElem,
+ size_t NumElems = (Packed ? NumBits : NumBits /
sizeof(VecElem))>
+ PredRegT<VecElem, NumElems, Packed, true> as() const
+ {
+ static_assert((Packed && NumElems <= NumBits) ||
+ (!Packed &&
+ NumBits % sizeof(VecElem) == 0 &&
+ sizeof(VecElem) * NumElems <= NumBits),
+ "Container size incompatible with view size");
+ return PredRegT<VecElem, NumElems, Packed, true>(*this);
+ }
+
+ template <typename VecElem,
+ size_t NumElems = (Packed ? NumBits : NumBits /
sizeof(VecElem))>
+ PredRegT<VecElem, NumElems, Packed, false> as()
+ {
+ static_assert((Packed && NumElems <= NumBits) ||
+ (!Packed &&
+ NumBits % sizeof(VecElem) == 0 &&
+ sizeof(VecElem) * NumElems <= NumBits),
+ "Container size incompatible with view size");
+ return PredRegT<VecElem, NumElems, Packed, false>(*this);
+ }
+ /// @}
+};
+
+/// Helper functions used for serialization/de-serialization
+template <size_t NumBits, bool Packed>
+inline bool
+to_number(const std::string& value, PredRegContainer<NumBits, Packed>& p)
+{
+ int i = 0;
+ for (const auto& c: value) {
+ p[i] = (c == '1');
+ }
+ return true;
+}
+
+#endif // __ARCH_GENERIC_PRED_REG_HH__
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index a65149f..b4d0240 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -490,6 +490,9 @@
def isVecElem(self):
return 0

+ def isPredReg(self):
+ return 0
+
def isPCState(self):
return 0

@@ -793,10 +796,9 @@

wb = '''
if (traceData) {
- warn_once("Vectors not supported yet in tracedata");
- /*traceData->setData(final_val);*/
+ traceData->setData(tmp_d%d);
}
- '''
+ ''' % self.dest_reg_idx
return wb

def finalize(self, predRead, predWrite):
@@ -849,6 +851,88 @@
(self.dest_reg_idx, self.base_name))
return c_write

+class PredRegOperand(Operand):
+ reg_class = 'PredRegClass'
+
+ def __init__(self, parser, full_name, ext, is_src, is_dest):
+ Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
+ self.parser = parser
+
+ def isReg(self):
+ return 1
+
+ def isPredReg(self):
+ return 1
+
+ def makeDecl(self):
+ return ''
+
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
+ if self.is_src:
+ c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
+
+ if self.is_dest:
+ c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
+ c_dest += '\n\t_numPredDestRegs++;'
+
+ return c_src + c_dest
+
+ def makeRead(self, predRead):
+ func = 'readPredRegOperand'
+ if self.read_code != None:
+ return self.buildReadCode(func)
+
+ if predRead:
+ rindex = '_sourceIndex++'
+ else:
+ rindex = '%d' % self.src_reg_idx
+
+ c_read = '\t\t%s& tmp_s%s = xc->%s(this, %s);\n' % (
+ 'const TheISA::PredRegContainer', rindex, func, rindex)
+ if self.ext:
+ c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % (
+ self.base_name, rindex,
+ self.parser.operandTypeMap[self.ext])
+ return c_read
+
+ def makeReadW(self, predWrite):
+ func = 'getWritablePredRegOperand'
+ if self.read_code != None:
+ return self.buildReadCode(func)
+
+ if predWrite:
+ rindex = '_destIndex++'
+ else:
+ rindex = '%d' % self.dest_reg_idx
+
+ c_readw = '\t\t%s& tmp_d%s = xc->%s(this, %s);\n' % (
+ 'TheISA::PredRegContainer', rindex, func, rindex)
+ if self.ext:
+ c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' % (
+ self.base_name, rindex,
+ self.parser.operandTypeMap[self.ext])
+ return c_readw
+
+ def makeWrite(self, predWrite):
+ func = 'setPredRegOperand'
+ if self.write_code != None:
+ return self.buildWriteCode(func)
+
+ wb = '''
+ if (traceData) {
+ traceData->setData(tmp_d%d);
+ }
+ ''' % self.dest_reg_idx
+ return wb
+
+ def finalize(self, predRead, predWrite):
+ super(PredRegOperand, self).finalize(predRead, predWrite)
+ if self.is_dest:
+ self.op_rd = self.makeReadW(predWrite) + self.op_rd
+
class CCRegOperand(Operand):
reg_class = 'CCRegClass'

@@ -1102,6 +1186,7 @@
self.numFPDestRegs = 0
self.numIntDestRegs = 0
self.numVecDestRegs = 0
+ self.numPredDestRegs = 0
self.numCCDestRegs = 0
self.numMiscDestRegs = 0
self.memOperand = None
@@ -1125,6 +1210,8 @@
self.numIntDestRegs += 1
elif op_desc.isVecReg():
self.numVecDestRegs += 1
+ elif op_desc.isPredReg():
+ self.numPredDestRegs += 1
elif op_desc.isCCReg():
self.numCCDestRegs += 1
elif op_desc.isControlReg():
@@ -1333,6 +1420,7 @@
header += '\n\t_numFPDestRegs = 0;'
header += '\n\t_numVecDestRegs = 0;'
header += '\n\t_numVecElemDestRegs = 0;'
+ header += '\n\t_numPredDestRegs = 0;'
header += '\n\t_numIntDestRegs = 0;'
header += '\n\t_numCCDestRegs = 0;'

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 885ca2f..40c8b43 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -166,6 +166,12 @@
return reg;
}

+ int
+ flattenPredIndex(int reg) const
+ {
+ return reg;
+ }
+
// dummy
int
flattenCCIndex(int reg) const
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 55c2dee..e1d15fa 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -32,6 +32,7 @@
#ifndef __ARCH_MIPS_REGISTERS_HH__
#define __ARCH_MIPS_REGISTERS_HH__

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/mips/generated/max_inst_regs.hh"
#include "base/logging.hh"
@@ -55,6 +56,8 @@
const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI &
LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+const int NumVecRegs = 1; // Not applicable to mips
+const int NumPredRegs = 1; // Not applicable to mips
const int NumCCRegs = 0;

const uint32_t MIPS32_QNAN = 0x7fbfffff;
@@ -290,14 +293,22 @@
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

-// dummy typedefs since we don't have vector regs
+// dummy typedefs and constants - not applicable to mips
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// dummy typedefs and constants - not applicable to mips
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

} // namespace MipsISA

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 3d27d95..5a5a841 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -40,6 +40,7 @@
#ifndef __ARCH_NULL_REGISTERS_HH__
#define __ARCH_NULL_REGISTERS_HH__

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/types.hh"
#include "base/types.hh"
@@ -53,14 +54,22 @@
typedef uint64_t MiscReg;
const RegIndex ZeroReg = 0;

-// dummy typedefs since we don't have vector regs
+// Dummy typedefs and constants - not applicable to null
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// Dummy typedefs and constants - not applicable to null
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

}

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 9769f8f..5803317 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -113,6 +113,12 @@
return reg;
}

+ int
+ flattenPredIndex(int reg) const
+ {
+ return reg;
+ }
+
// dummy
int
flattenCCIndex(int reg) const
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index adbaae5..abe3de2 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -31,6 +31,7 @@
#ifndef __ARCH_POWER_REGISTERS_HH__
#define __ARCH_POWER_REGISTERS_HH__

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/power/generated/max_inst_regs.hh"
#include "arch/power/miscregs.hh"
@@ -54,14 +55,22 @@
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

-// dummy typedefs since we don't have vector regs
+// Dummy typedefs and constants - not applicable to Power
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// Dummy typedefs and constants - not applicable to Power
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

// Constants Related to the number of registers
const int NumIntArchRegs = 32;
@@ -75,6 +84,8 @@

const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+const int NumVecRegs = 1; // Not applicable to Power
+const int NumPredRegs = 1; // Not applicable to Power
const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;

diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index f96b072..e136c2d 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -84,6 +84,7 @@
int flattenFloatIndex(int reg) const { return reg; }
int flattenVecIndex(int reg) const { return reg; }
int flattenVecElemIndex(int reg) const { return reg; }
+ int flattenPredIndex(int reg) const { return reg; }
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index bd95cf8..f5fca6d 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -51,6 +51,7 @@
#include <string>
#include <vector>

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/types.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/isa_traits.hh"
@@ -69,19 +70,32 @@
typedef uint8_t CCReg; // Not applicable to Riscv
typedef uint64_t MiscReg;

-// dummy typedefs since we don't have vector regs
-const unsigned NumVecElemPerVecReg = 2;
+// Dummy typedefs and constants - not applicable to Riscv
+constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;

+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);
+
const int NumIntArchRegs = 32;
const int NumMicroIntRegs = 1;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
const int NumFloatRegs = 32;
+
// This has to be one to prevent warnings that are treated as errors
const unsigned NumVecRegs = 1;
+const int NumPredRegs = 1; // Not applicable to Riscv
+
const int NumCCRegs = 0;

// Semantically meaningful register indices
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 82fee0d..c212efe 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -235,6 +235,12 @@
return reg;
}

+ int
+ flattenPredIndex(int reg) const
+ {
+ return reg;
+ }
+
// dummy
int
flattenCCIndex(int reg) const
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index a7f4d2a..1a3d5d4 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -32,6 +32,7 @@
#ifndef __ARCH_SPARC_REGISTERS_HH__
#define __ARCH_SPARC_REGISTERS_HH__

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/sparc/generated/max_inst_regs.hh"
#include "arch/sparc/miscregs.hh"
@@ -53,14 +54,22 @@
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

-// dummy typedefs since we don't have vector regs
+// Dummy typedefs and constants - not applicable to Sparc
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// Dummy typedefs and constants - not applicable to Sparc
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
@@ -75,6 +84,8 @@

const int NumIntArchRegs = 32;
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+const int NumVecRegs = 1; // Not applicable to Sparc
+const int NumPredRegs = 1; // Not applicable to Sparc
const int NumCCRegs = 0;

const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index b61face..44f48e5 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -117,6 +117,12 @@
}

int
+ flattenPredIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
flattenCCIndex(int reg) const
{
return reg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c2977f8..1cf9f5e 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,6 +41,7 @@
#ifndef __ARCH_X86_REGISTERS_HH__
#define __ARCH_X86_REGISTERS_HH__

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/x86/generated/max_inst_regs.hh"
#include "arch/x86/regs/int.hh"
@@ -77,6 +78,9 @@
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
};

+const int NumVecRegs = 1; // Not applicable to x86
+const int NumPredRegs = 1; // Not applicable to x86
+
// semantically meaningful register indices
//There is no such register in X86
const int ZeroReg = NUM_INTREGS;
@@ -94,14 +98,22 @@
typedef uint64_t CCReg;
typedef uint64_t MiscReg;

-// dummy typedefs since we don't have vector regs
+// Dummy typedefs and constants - not applicable to Riscv
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// This has to be one to prevent warnings that are treated as errors
-constexpr unsigned NumVecRegs = 1;
+constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem);
+
+// Dummy typedefs and constants - not applicable to Riscv
+constexpr bool PredRegHasPackedRepr = false;
+using PredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, false>;
+using ConstPredReg = ::PredRegT<VecElem, NumVecElemPerVecReg,
+ PredRegHasPackedRepr, true>;
+using PredRegContainer = PredReg::Container;
+constexpr size_t PredRegSizeBits = NumVecElemPerVecReg * sizeof(VecElem);

//These floating point types are correct for mmx, but not
//technically for x87 (80 bits) or at all for xmm (128 bits)
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b4431da..52d2834 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011,2013,2016 ARM Limited
+ * Copyright (c) 2011, 2013, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -592,6 +592,7 @@
int8_t numVecElemDestRegs() const {
return staticInst->numVecElemDestRegs();
}
+ int8_t numPredDestRegs() const { return staticInst->numPredDestRegs();
}

/** Returns the logical register index of the i'th destination
register. */
const RegId& destRegIdx(int i) const { return
staticInst->destRegIdx(i); }
@@ -646,6 +647,16 @@
InstResult::ResultType::VecElem));
}
}
+
+ /** Predicate result. */
+ template<typename T>
+ void setPredResult(T&& t)
+ {
+ if (instFlags[RecordResult]) {
+ instResult.push(InstResult(std::forward<T>(t),
+ InstResult::ResultType::PredReg));
+ }
+ }
/** @} */

/** Records an integer register being set to a value. */
@@ -686,6 +697,13 @@
setVecElemResult(val);
}

+ /** Record a vector register being set to a value */
+ void setPredRegOperand(const StaticInst *si, int idx,
+ const PredRegContainer& val)
+ {
+ setPredResult(val);
+ }
+
/** Records that one of the source registers is ready. */
void markSrcRegReady();

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index cb87f62..8b2395e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2016 ARM Limited
+ * Copyright (c) 2011, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -316,6 +316,22 @@
return thread->readVecElem(reg);
}

+ const PredRegContainer& readPredRegOperand(const StaticInst *si,
+ int idx) const override
+ {
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread->readPredReg(reg);
+ }
+
+ PredRegContainer& getWritablePredRegOperand(const StaticInst *si,
+ int idx) override
+ {
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread->getWritablePredReg(reg);
+ }
+
CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -344,6 +360,13 @@
InstResult::ResultType::VecElem));
}

+ template<typename T>
+ void setPredResult(T&& t)
+ {
+ result.push(InstResult(std::forward<T>(t),
+ InstResult::ResultType::PredReg));
+ }
+
void setIntRegOperand(const StaticInst *si, int idx,
IntReg val) override
{
@@ -397,6 +420,15 @@
setVecElemResult(val);
}

+ void setPredRegOperand(const StaticInst *si, int idx,
+ const PredRegContainer& val) override
+ {
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ thread->setPredReg(reg, val);
+ setPredResult(val);
+ }
+
bool readPredicate() const override { return thread->readPredicate(); }

void setPredicate(bool val) override
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 975bd9f..7db3973 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -264,6 +264,12 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }

+ const PredRegContainer& readPredReg(const RegId& reg) const override
+ { return actualTC->readPredReg(reg); }
+
+ PredRegContainer& getWritablePredReg(const RegId& reg) override
+ { return actualTC->getWritablePredReg(reg); }
+
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }

@@ -297,6 +303,12 @@
checkerTC->setVecElem(reg, val);
}

+ void setPredReg(const RegId& reg, const PredRegContainer& val) override
+ {
+ actualTC->setPredReg(reg, val);
+ checkerTC->setPredReg(reg, val);
+ }
+
void setCCReg(int reg_idx, CCReg val)
{
actualTC->setCCReg(reg_idx, val);
@@ -414,6 +426,15 @@
const ElemIndex& elem_idx, const VecElem& val)
{ actualTC->setVecElemFlat(idx, elem_idx, val); }

+ const PredRegContainer& readPredRegFlat(int idx) const override
+ { return actualTC->readPredRegFlat(idx); }
+
+ PredRegContainer& getWritablePredRegFlat(int idx) override
+ { return actualTC->getWritablePredRegFlat(idx); }
+
+ void setPredRegFlat(int idx, const PredRegContainer& val) override
+ { actualTC->setPredRegFlat(idx, val); }
+
CCReg readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index bc9b486..293e139 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -81,6 +81,7 @@
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
+ using PredRegContainer = TheISA::PredRegContainer;

public:
/**
@@ -180,6 +181,22 @@
const VecElem val) = 0;
/** @} */

+ /** Predicate registers interface. */
+ /** @{ */
+ /** Reads source predicate register operand. */
+ virtual const PredRegContainer&
+ readPredRegOperand(const StaticInst *si, int idx) const = 0;
+
+ /** Gets destination predicate register operand for modification. */
+ virtual PredRegContainer&
+ getWritablePredRegOperand(const StaticInst *si, int idx) = 0;
+
+ /** Sets a destination predicate register operand to a value. */
+ virtual void
+ setPredRegOperand(const StaticInst *si, int idx,
+ const PredRegContainer& val) = 0;
+ /** @} */
+
/**
* @{
* @name Condition Code Registers
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index 9b6a23d..6f5c141 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -48,12 +48,14 @@
class InstResult {
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
+ using PredRegContainer = TheISA::PredRegContainer;
public:
union MultiResult {
uint64_t integer;
double dbl;
VecRegContainer vector;
VecElem vecElem;
+ PredRegContainer pred;
MultiResult() {}
};

@@ -61,6 +63,7 @@
Scalar,
VecElem,
VecReg,
+ PredReg,
NumResultTypes,
Invalid
};
@@ -87,6 +90,9 @@
/** Vector result. */
explicit InstResult(const VecRegContainer& v, const ResultType& t)
: type(t) { result.vector = v; }
+ /** Predicate result. */
+ explicit InstResult(const PredRegContainer& v, const ResultType& t)
+ : type(t) { result.pred = v; }

InstResult& operator=(const InstResult& that) {
type = that.type;
@@ -104,6 +110,10 @@
case ResultType::VecReg:
result.vector = that.result.vector;
break;
+ case ResultType::PredReg:
+ result.pred = that.result.pred;
+ break;
+
default:
panic("Assigning result from unknown result type");
break;
@@ -124,6 +134,8 @@
return result.vecElem == that.result.vecElem;
case ResultType::VecReg:
return result.vector == that.result.vector;
+ case ResultType::PredReg:
+ return result.pred == that.result.pred;
case ResultType::Invalid:
return false;
default:
@@ -143,6 +155,8 @@
bool isVector() const { return type == ResultType::VecReg; }
/** Is this a vector element result?. */
bool isVecElem() const { return type == ResultType::VecElem; }
+ /** Is this a predicate result?. */
+ bool isPred() const { return type == ResultType::PredReg; }
/** Is this a valid result?. */
bool isValid() const { return type != ResultType::Invalid; }
/** @} */
@@ -177,6 +191,14 @@
panic_if(!isVecElem(), "Converting scalar (or invalid) to
vector!!");
return result.vecElem;
}
+
+ const PredRegContainer&
+ asPred() const
+ {
+ panic_if(!isPred(), "Converting scalar (or invalid) to
predicate!!");
+ return result.pred;
+ }
+
/** @} */
};

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 238d113..bc86276 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2014, 2016 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -169,6 +169,22 @@
return thread.readVecElem(reg);
}

+ const TheISA::PredRegContainer&
+ readPredRegOperand(const StaticInst *si, int idx) const override
+ {
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread.readPredReg(reg);
+ }
+
+ TheISA::PredRegContainer&
+ getWritablePredRegOperand(const StaticInst *si, int idx) override
+ {
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread.getWritablePredReg(reg);
+ }
+
void
setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
{
@@ -204,6 +220,15 @@
thread.setVecReg(reg, val);
}

+ void
+ setPredRegOperand(const StaticInst *si, int idx,
+ const TheISA::PredRegContainer& val)
+ {
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ thread.setPredReg(reg, val);
+ }
+
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index c56d3b3..938a032 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, 2016 ARM Limited
+ * Copyright (c) 2013-2014, 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -77,6 +77,11 @@
TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
ret = true;
break;
+ case PredRegClass:
+ scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
+ TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
+ ret = true;
+ break;
case CCRegClass:
scoreboard_index = TheISA::NumIntRegs + reg.index();
ret = true;
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index 9e42c2a..0315f7a 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, 2016 ARM Limited
+ * Copyright (c) 2013-2014, 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -94,7 +94,7 @@
Scoreboard(const std::string &name) :
Named(name),
numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
- TheISA::NumFloatRegs + TheISA::NumVecRegs),
+ TheISA::NumFloatRegs + TheISA::NumVecRegs +
TheISA::NumPredRegs),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, 0),
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index b8152f6..434f7ce 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016 ARM Limited
+# Copyright (c) 2016-2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -141,6 +141,8 @@
_defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
"registers")
+ numPhysPredRegs = Param.Unsigned(32, "Number of physical predicate "
+ "registers")
numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
"Number of physical cc registers")
numIQEntries = Param.Unsigned(64, "Number of instruction queue
entries")
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index f5be5a8..67411cd 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2016 ARM Limited
+ * Copyright (c) 2011, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -121,6 +121,9 @@
/** @Return true if it is a vector element physical register. */
bool isVectorPhysElem() const { return isVecElem(); }

+ /** @return true if it is a predicate physical register. */
+ bool isPredPhysReg() const { return isPredReg(); }
+
/** @Return true if it is a condition-code physical register. */
bool isMiscPhysReg() const { return isMiscReg(); }

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2f79345..f2fbae5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -159,6 +159,7 @@
regFile(params->numPhysIntRegs,
params->numPhysFloatRegs,
params->numPhysVecRegs,
+ params->numPhysPredRegs,
params->numPhysCCRegs,
vecMode),

@@ -258,6 +259,7 @@
assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
+ assert(params->numPhysPredRegs >= numThreads * TheISA::NumPredRegs);
assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);

rename.setScoreboard(&scoreboard);
@@ -325,6 +327,13 @@
}
}

+ for (RegIndex ridx = 0; ridx < TheISA::NumPredRegs; ++ridx) {
+ PhysRegIdPtr phys_reg = freeList.getPredReg();
+ renameMap[tid].setEntry(RegId(PredRegClass, ridx), phys_reg);
+ commitRenameMap[tid].setEntry(
+ RegId(PredRegClass, ridx), phys_reg);
+ }
+
for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
PhysRegIdPtr phys_reg = freeList.getCCReg();
renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
@@ -538,6 +547,16 @@
.desc("number of vector regfile writes")
.prereq(vecRegfileWrites);

+ predRegfileReads
+ .name(name() + ".pred_regfile_reads")
+ .desc("number of predicate regfile reads")
+ .prereq(predRegfileReads);
+
+ predRegfileWrites
+ .name(name() + ".pred_regfile_writes")
+ .desc("number of predicate regfile writes")
+ .prereq(predRegfileWrites);
+
ccRegfileReads
.name(name() + ".cc_regfile_reads")
.desc("number of cc regfile reads")
@@ -884,6 +903,14 @@
freeList.addReg(phys_reg);
}

+ // Unbind Float Regs from Rename Map
+ for (unsigned preg = 0; preg < TheISA::NumPredRegs; preg++) {
+ PhysRegIdPtr phys_reg = renameMap[tid].lookup(
+ RegId(PredRegClass,
preg));
+ scoreboard.unsetReg(phys_reg);
+ freeList.addReg(phys_reg);
+ }
+
// Unbind condition-code Regs from Rename Map
for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
reg_id.index()++) {
@@ -1326,6 +1353,24 @@
}

template <class Impl>
+auto
+FullO3CPU<Impl>::readPredReg(PhysRegIdPtr phys_reg) const
+ -> const PredRegContainer&
+{
+ predRegfileReads++;
+ return regFile.readPredReg(phys_reg);
+}
+
+template <class Impl>
+auto
+FullO3CPU<Impl>::getWritablePredReg(PhysRegIdPtr phys_reg)
+ -> PredRegContainer&
+{
+ predRegfileWrites++;
+ return regFile.getWritablePredReg(phys_reg);
+}
+
+template <class Impl>
CCReg
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
@@ -1375,6 +1420,14 @@

template <class Impl>
void
+FullO3CPU<Impl>::setPredReg(PhysRegIdPtr phys_reg, const PredRegContainer&
val)
+{
+ predRegfileWrites++;
+ regFile.setPredReg(phys_reg, val);
+}
+
+template <class Impl>
+void
FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
{
ccRegfileWrites++;
@@ -1445,6 +1498,26 @@
}

template <class Impl>
+auto
+FullO3CPU<Impl>::readArchPredReg(int reg_idx, ThreadID tid) const
+ -> const PredRegContainer&
+{
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
+ RegId(PredRegClass, reg_idx));
+ return readPredReg(phys_reg);
+}
+
+template <class Impl>
+auto
+FullO3CPU<Impl>::getWritableArchPredReg(int reg_idx, ThreadID tid)
+ -> PredRegContainer&
+{
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
+ RegId(PredRegClass, reg_idx));
+ return getWritablePredReg(phys_reg);
+}
+
+template <class Impl>
CCReg
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
@@ -1510,6 +1583,16 @@

template <class Impl>
void
+FullO3CPU<Impl>::setArchPredReg(int reg_idx, const PredRegContainer& val,
+ ThreadID tid)
+{
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
+ RegId(PredRegClass, reg_idx));
+ setPredReg(phys_reg, val);
+}
+
+template <class Impl>
+void
FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
{
ccRegfileWrites++;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 19b9a34..74dc327 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013, 2016 ARM Limited
+ * Copyright (c) 2011-2013, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -107,6 +107,8 @@
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;

+ using PredRegContainer = TheISA::PredRegContainer;
+
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;

@@ -445,6 +447,10 @@

const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;

+ const PredRegContainer& readPredReg(PhysRegIdPtr reg_idx) const;
+
+ PredRegContainer& getWritablePredReg(PhysRegIdPtr reg_idx);
+
TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);

void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
@@ -457,6 +463,8 @@

void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);

+ void setPredReg(PhysRegIdPtr reg_idx, const PredRegContainer& val);
+
void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);

uint64_t readArchIntReg(int reg_idx, ThreadID tid);
@@ -493,6 +501,10 @@
const VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid)
const;

+ const PredRegContainer& readArchPredReg(int reg_idx, ThreadID tid)
const;
+
+ PredRegContainer& getWritableArchPredReg(int reg_idx, ThreadID tid);
+
TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);

/** Architectural register accessors. Looks up in the commit
@@ -506,6 +518,9 @@

void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);

+ void setArchPredReg(int reg_idx, const PredRegContainer& val,
+ ThreadID tid);
+
void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID
tid);

void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
@@ -795,6 +810,9 @@
//number of vector register file accesses
mutable Stats::Scalar vecRegfileReads;
Stats::Scalar vecRegfileWrites;
+ //number of predicate register file accesses
+ mutable Stats::Scalar predRegfileReads;
+ Stats::Scalar predRegfileWrites;
//number of CC register file accesses
Stats::Scalar ccRegfileReads;
Stats::Scalar ccRegfileWrites;
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 47dc830..39a418b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -73,6 +73,7 @@
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;
+ using PredRegContainer = TheISA::PredRegContainer;

/** Misc register type. */
typedef TheISA::MiscReg MiscReg;
@@ -233,6 +234,10 @@
this->setVecElemOperand(this->staticInst.get(), idx,
this->cpu->readVecElem(prev_phys_reg));
break;
+ case PredRegClass:
+ this->setPredRegOperand(this->staticInst.get(), idx,
+ this->cpu->readPredReg(prev_phys_reg));
+ break;
case CCRegClass:
this->setCCRegOperand(this->staticInst.get(), idx,
this->cpu->readCCReg(prev_phys_reg));
@@ -366,6 +371,18 @@
return this->cpu->readVecElem(this->_srcRegIdx[idx]);
}

+ const PredRegContainer&
+ readPredRegOperand(const StaticInst *si, int idx) const override
+ {
+ return this->cpu->readPredReg(this->_srcRegIdx[idx]);
+ }
+
+ PredRegContainer&
+ getWritablePredRegOperand(const StaticInst *si, int idx) override
+ {
+ return this->cpu->getWritablePredReg(this->_destRegIdx[idx]);
+ }
+
CCReg readCCRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readCCReg(this->_srcRegIdx[idx]);
@@ -409,6 +426,14 @@
BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
}

+ void
+ setPredRegOperand(const StaticInst *si, int idx,
+ const PredRegContainer& val) override
+ {
+ this->cpu->setPredReg(this->_destRegIdx[idx], val);
+ BaseDynInst<Impl>::setPredRegOperand(si, idx, val);
+ }
+
void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
{
this->cpu->setCCReg(this->_destRegIdx[idx], val);
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 3ad08ee..e270fef 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -138,6 +138,9 @@
SimpleFreeList vecElemList;
/** @} */

+ /** The list of free predicate registers. */
+ SimpleFreeList predList;
+
/** The list of free condition-code registers. */
SimpleFreeList ccList;

@@ -183,6 +186,9 @@
/** Gets a free vector elemenet register. */
PhysRegIdPtr getVecElem() { return vecElemList.getReg(); }

+ /** Gets a free predicate register. */
+ PhysRegIdPtr getPredReg() { return predList.getReg(); }
+
/** Gets a free cc register. */
PhysRegIdPtr getCCReg() { return ccList.getReg(); }

@@ -207,6 +213,9 @@
vecElemList.addReg(freed_reg);
}

+ /** Adds a predicate register back to the free list. */
+ void addPredReg(PhysRegIdPtr freed_reg) { predList.addReg(freed_reg); }
+
/** Adds a cc register back to the free list. */
void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }

@@ -222,6 +231,9 @@
/** Checks if there are any free vector registers. */
bool hasFreeVecElems() const { return vecElemList.hasFreeRegs(); }

+ /** Checks if there are any free predicate registers. */
+ bool hasFreePredRegs() const { return predList.hasFreeRegs(); }
+
/** Checks if there are any free cc registers. */
bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }

@@ -234,6 +246,9 @@
/** Returns the number of free vector registers. */
unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }

+ /** Returns the number of free predicate registers. */
+ unsigned numFreePredRegs() const { return predList.numFreeRegs(); }
+
/** Returns the number of free cc registers. */
unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
};
@@ -264,6 +279,9 @@
case VecElemClass:
vecElemList.addRegs(first, last);
break;
+ case PredRegClass:
+ predList.addRegs(first, last);
+ break;
case CCRegClass:
ccList.addRegs(first, last);
break;
@@ -294,6 +312,9 @@
case VecElemClass:
vecElemList.addReg(freed_reg);
break;
+ case PredRegClass:
+ predList.addReg(freed_reg);
+ break;
case CCRegClass:
ccList.addReg(freed_reg);
break;
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 252afbe..75a2573 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2014 ARM Limited
+ * Copyright (c) 2011-2014, 2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -102,6 +102,7 @@
numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
params->numPhysVecRegs +
params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
+ params->numPhysPredRegs +
params->numPhysCCRegs;

//Create an entry for each physical register within the
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 2f41e2a..b48d38a 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -52,22 +52,26 @@
PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs,
unsigned _numPhysicalVecRegs,
+ unsigned _numPhysicalPredRegs,
unsigned _numPhysicalCCRegs,
VecMode vmode)
: intRegFile(_numPhysicalIntRegs),
floatRegFile(_numPhysicalFloatRegs),
vectorRegFile(_numPhysicalVecRegs),
+ predRegFile(_numPhysicalPredRegs),
ccRegFile(_numPhysicalCCRegs),
numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalVecRegs(_numPhysicalVecRegs),
numPhysicalVecElemRegs(_numPhysicalVecRegs *
NumVecElemPerVecReg),
+ numPhysicalPredRegs(_numPhysicalPredRegs),
numPhysicalCCRegs(_numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
+ _numPhysicalFloatRegs
+ _numPhysicalVecRegs
+ _numPhysicalVecRegs * NumVecElemPerVecReg
+ + _numPhysicalPredRegs
+ _numPhysicalCCRegs),
vecMode(vmode)
{
@@ -108,6 +112,12 @@
}
}

+ // The next batch of the registers are the predicate physical
+ // registers; put them onto the predicate free list.
+ for (phys_reg = 0; phys_reg < numPhysicalPredRegs; phys_reg++) {
+ predRegIds.emplace_back(PredRegClass, phys_reg, flat_reg_idx++);
+ }
+
// The rest of the registers are the condition-code physical
// registers; put them onto the condition-code free list.
for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
@@ -159,6 +169,13 @@
else
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());

+ // The next batch of the registers are the predicate physical
+ // registers; put them onto the predicate free list.
+ for (reg_idx = 0; reg_idx < numPhysicalPredRegs; reg_idx++) {
+ assert(predRegIds[reg_idx].index() == reg_idx);
+ }
+ freeList->addRegs(predRegIds.begin(), predRegIds.end());
+
// The rest of the registers are the condition-code physical
// registers; put them onto the condition-code free list.
for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
@@ -191,6 +208,8 @@
return std::make_pair(vecRegIds.begin(), vecRegIds.end());
case VecElemClass:
return std::make_pair(vecElemIds.begin(), vecElemIds.end());
+ case PredRegClass:
+ return std::make_pair(predRegIds.begin(), predRegIds.end());
case CCRegClass:
return std::make_pair(ccRegIds.begin(), ccRegIds.end());
case MiscRegClass:
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 7feec93..013bd6a 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -73,6 +73,7 @@
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
using VecMode = Enums::VecRegRenameMode;
+ using PredRegContainer = TheISA::PredRegContainer;
public:
using IdRange = std::pair<PhysIds::const_iterator,
PhysIds::const_iterator>;
@@ -97,6 +98,10 @@
std::vector<PhysRegId> vecRegIds;
std::vector<PhysRegId> vecElemIds;

+ /** Predicate register file. */
+ std::vector<PredRegContainer> predRegFile;
+ std::vector<PhysRegId> predRegIds;
+
/** Condition-code register file. */
std::vector<CCReg> ccRegFile;
std::vector<PhysRegId> ccRegIds;
@@ -125,6 +130,11 @@
unsigned numPhysicalVecElemRegs;

/**
+ * Number of physical predicate registers
+ */
+ unsigned numPhysicalPredRegs;
+
+ /**
* Number of physical CC registers
*/
unsigned numPhysicalCCRegs;
@@ -143,6 +153,7 @@
PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs,
unsigned _numPhysicalVecRegs,
+ unsigned _numPhysicalPredRegs,
unsigned _numPhysicalCCRegs,
VecMode vmode
);
@@ -162,6 +173,8 @@
unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
/** @return the number of vector physical registers. */
unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
+ /** @return the number of predicate physical registers. */
+ unsigned numPredPhysRegs() const { return numPhysicalPredRegs; }

/** @return the number of vector physical registers. */
unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
@@ -219,7 +232,7 @@

DPRINTF(IEW, "RegFile: Access to vector register %i, has "
"data %s\n", int(phys_reg->index()),
- vectorRegFile[phys_reg->index()].as<VecElem>().print());
+ vectorRegFile[phys_reg->index()].print());

return vectorRegFile[phys_reg->index()];
}
@@ -274,6 +287,24 @@
return val;
}

+ /** Reads a predicate register. */
+ const PredRegContainer& readPredReg(PhysRegIdPtr phys_reg) const
+ {
+ assert(phys_reg->isPredPhysReg());
+
+ DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
+ "data %s\n", int(phys_reg->index()),
+ predRegFile[phys_reg->index()].print());
+
+ return predRegFile[phys_reg->index()];
+ }
+
+ PredRegContainer& getWritablePredReg(PhysRegIdPtr phys_reg)
+ {
+ /* const_cast for not duplicating code above. */
+ return const_cast<PredRegContainer&>(readPredReg(phys_reg));
+ }
+
/** Reads a condition-code register. */
CCReg readCCReg(PhysRegIdPtr phys_reg)
{
@@ -344,6 +375,17 @@
val;
}

+ /** Sets a predicate register to the given value. */
+ void setPredReg(PhysRegIdPtr phys_reg, const PredRegContainer& val)
+ {
+ assert(phys_reg->isPredPhysReg());
+
+ DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
+ int(phys_reg->index()), val.print());
+
+ predRegFile[phys_reg->index()] = val;
+ }
+
/** Sets a condition-code register to the given value. */
void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
{
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index bd5e72d..022fc05 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -514,6 +514,7 @@
Stats::Scalar intRenameLookups;
Stats::Scalar fpRenameLookups;
Stats::Scalar vecRenameLookups;
+ Stats::Scalar predRenameLookups;
/** Stat for total number of committed renaming mappings. */
Stats::Scalar renameCommittedMaps;
/** Stat for total number of mappings that were undone due to a
squash. */
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 4331b6d..700ea60 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -196,6 +196,10 @@
.name(name() + ".vec_rename_lookups")
.desc("Number of vector rename lookups")
.prereq(vecRenameLookups);
+ predRenameLookups
+ .name(name() + ".pred_rename_lookups")
+ .desc("Number of predicate rename lookups")
+ .prereq(predRenameLookups);
}

template <class Impl>
@@ -659,6 +663,7 @@
inst->numFPDestRegs(),
inst->numVecDestRegs(),
inst->numVecElemDestRegs(),
+ inst->numPredDestRegs(),
inst->numCCDestRegs())) {
DPRINTF(Rename, "Blocking due to lack of free "
"physical registers to rename to.\n");
@@ -1041,6 +1046,9 @@
case VecRegClass:
vecRenameLookups++;
break;
+ case PredRegClass:
+ predRenameLookups++;
+ break;
case CCRegClass:
case MiscRegClass:
break;
@@ -1256,7 +1264,7 @@
}

DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
- "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n",
+ "Free LQ: %i, Free SQ: %i,
FreeRM %i(%i %i %i %i %i)\n",
tid,
freeEntries[tid].iqEntries,
freeEntries[tid].robEntries,
@@ -1266,6 +1274,7 @@
renameMap[tid]->numFreeIntEntries(),
renameMap[tid]->numFreeFloatEntries(),
renameMap[tid]->numFreeVecEntries(),
+ renameMap[tid]->numFreePredEntries(),
renameMap[tid]->numFreeCCEntries());

DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 1194b55..c6a49e4 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -120,6 +120,8 @@
vecElemMap.init(TheISA::NumVecRegs * NVecElems,
&(freeList->vecElemList), (RegIndex)-1);

+ predMap.init(TheISA::NumPredRegs, &(freeList->predList), (RegIndex)-1);
+
ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);

}
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index ab909f0..ee36a3e 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016 ARM Limited
+ * Copyright (c) 2015-2017 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -173,6 +173,7 @@
private:
static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
using VecReg = TheISA::VecReg;
+ using PredReg = TheISA::PredReg;

/** The integer register rename map */
SimpleRenameMap intMap;
@@ -189,6 +190,9 @@
/** The vector element register rename map */
SimpleRenameMap vecElemMap;

+ /** The predicate register rename map */
+ SimpleRenameMap predMap;
+
using VecMode = Enums::VecRegRenameMode;
VecMode vecMode;

@@ -236,6 +240,8 @@
case VecElemClass:
assert(vecMode == Enums::Elem);
return vecElemMap.rename(arch_reg);
+ case PredRegClass:
+ return predMap.rename(arch_reg);
case CCRegClass:
return ccMap.rename(arch_reg);
case MiscRegClass:
@@ -277,6 +283,9 @@
assert(vecMode == Enums::Elem);
return vecElemMap.lookup(arch_reg);

+ case PredRegClass:
+ return predMap.lookup(arch_reg);
+
case CCRegClass:
return ccMap.lookup(arch_reg);

@@ -320,6 +329,10 @@
assert(vecMode == Enums::Elem);
return vecElemMap.setEntry(arch_reg, phys_reg);

+ case PredRegClass:
+ assert(phys_reg->isPredPhysReg());
+ return predMap.setEntry(arch_reg, phys_reg);
+
case CCRegClass:
assert(phys_reg->isCCPhysReg());
return ccMap.setEntry(arch_reg, phys_reg);
@@ -346,10 +359,11 @@
*/
unsigned numFreeEntries() const
{
- return std::min(
+ return std::min(std::min(
std::min(intMap.numFreeEntries(),
floatMap.numFreeEntries()),
vecMode == Enums::Full ? vecMap.numFreeEntries()
- : vecElemMap.numFreeEntries());
+ : vecElemMap.numFreeEntries()),
+ predMap.numFreeEntries());
}

unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
@@ -360,18 +374,21 @@
? vecMap.numFreeEntries()
: vecElemMap.numFreeEntries();
}
+ unsigned numFreePredEntries() const { return predMap.numFreeEntries();
}
unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }

/**
* Return whether there are enough registers to serve the request.
*/
bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t
vectorRegs,
- uint32_t vecElemRegs, uint32_t ccRegs) const
+ uint32_t vecElemRegs, uint32_t predRegs,
+ uint32_t ccRegs) const
{
return intRegs <= intMap.numFreeEntries() &&
floatRegs <= floatMap.numFreeEntries() &&
vectorRegs <= vecMap.numFreeEntries() &&
vecElemRegs <= vecElemMap.numFreeEntries() &&
+ predRegs <= predMap.numFreeEntries() &&
ccRegs <= ccMap.numFreeEntries();
}
/**
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 2256a8a..4246415 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -258,6 +258,14 @@
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
}

+ virtual const PredRegContainer& readPredReg(const RegId& id) const {
+ return readPredRegFlat(flattenRegId(id).index());
+ }
+
+ virtual PredRegContainer& getWritablePredReg(const RegId& id) {
+ return getWritablePredRegFlat(flattenRegId(id).index());
+ }
+
virtual CCReg readCCReg(int reg_idx) {
return readCCRegFlat(flattenRegId(RegId(CCRegClass,
reg_idx)).index());
@@ -286,6 +294,10 @@
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}

+ virtual void setPredReg(const RegId& reg, const PredRegContainer& val)
{
+ setPredRegFlat(flattenRegId(reg).index(), val);
+ }
+
virtual void setCCReg(int reg_idx, CCReg val) {
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(),
val);
}
@@ -393,6 +405,10 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val);

+ virtual const PredRegContainer& readPredRegFlat(int idx) const
override;
+ virtual PredRegContainer& getWritablePredRegFlat(int idx) override;
+ virtual void setPredRegFlat(int idx, const PredRegContainer& val)
override;
+
virtual CCReg readCCRegFlat(int idx);
virtual void setCCRegFlat(int idx, CCReg val);
};
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index d9f84fb..4db6728 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -236,6 +236,20 @@
}

template <class Impl>
+const TheISA::PredRegContainer&
+O3ThreadContext<Impl>::readPredRegFlat(int reg_id) const
+{
+ return cpu->readArchPredReg(reg_id, thread->threadId());
+}
+
+template <class Impl>
+TheISA::PredRegContainer&
+O3ThreadContext<Impl>::getWritablePredRegFlat(int reg_id)
+{
+ return cpu->getWritableArchPredReg(reg_id, thread->threadId());
+}
+
+template <class Impl>
TheISA::CCReg
O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
{
@@ -289,6 +303,15 @@

template <class Impl>
void
+O3ThreadContext<Impl>::setPredRegFlat(int reg_idx, const PredRegContainer&
val)
+{
+ cpu->setArchPredReg(reg_idx, val, thread->threadId());
+
+ conditionalSquash();
+}
+
+template <class Impl>
+void
O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
{
cpu->setArchCCReg(reg_idx, val, thread->threadId());
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index 16c1949..27f1f59 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,6 +47,7 @@
"FloatRegClass",
"VecRegClass",
"VecElemClass",
+ "PredRegClass",
"CCRegClass",
"MiscRegClass"
};
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 69da9cf..9c5bd8a 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -60,6 +60,7 @@
VecRegClass,
/** Vector Register Native Elem lane. */
VecElemClass,
+ PredRegClass,
CCRegClass, ///< Condition-code register
MiscRegClass ///< Control (misc) register
};
@@ -151,6 +152,9 @@
/** @Return true if it is a condition-code physical register. */
bool isVecElem() const { return regClass == VecElemClass; }

+ /** @Return true if it is a predicate physical register. */
+ bool isPredReg() const { return regClass == PredRegClass; }
+
/** @Return true if it is a condition-code physical register. */
bool isCCReg() const { return regClass == CCRegClass; }

@@ -179,6 +183,7 @@
case IntRegClass:
case FloatRegClass:
case VecRegClass:
+ case PredRegClass:
case CCRegClass:
case MiscRegClass:
return regIdx;
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 8ff18dd..814a7ee 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016 ARM Limited
+ * Copyright (c) 2014-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -124,6 +124,10 @@
mutable Stats::Scalar numVecRegReads;
Stats::Scalar numVecRegWrites;

+ // Number of predicate register file accesses
+ mutable Stats::Scalar numPredRegReads;
+ Stats::Scalar numPredRegWrites;
+
// Number of condition code register file accesses
Stats::Scalar numCCRegReads;
Stats::Scalar numCCRegWrites;
@@ -349,6 +353,33 @@
thread->setVecElem(reg, val);
}

+ const PredRegContainer&
+ readPredRegOperand(const StaticInst *si, int idx) const override
+ {
+ numPredRegReads++;
+ const RegId& reg = si->srcRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread->readPredReg(reg);
+ }
+
+ PredRegContainer&
+ getWritablePredRegOperand(const StaticInst *si, int idx) override
+ {
+ numPredRegWrites++;
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ return thread->getWritablePredReg(reg);
+ }
+
+ void setPredRegOperand(const StaticInst *si, int idx,
+ const PredRegContainer& val) override
+ {
+ numPredRegWrites++;
+ const RegId& reg = si->destRegIdx(idx);
+ assert(reg.isPredReg());
+ thread->setPredReg(reg, val);
+ }
+
CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3c64082..24d372c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -58,6 +58,7 @@
#include "debug/CCRegs.hh"
#include "debug/FloatRegs.hh"
#include "debug/IntRegs.hh"
+#include "debug/PredRegs.hh"
#include "debug/VecRegs.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
@@ -105,6 +106,7 @@
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
+ using PredRegContainer = TheISA::PredRegContainer;
public:
typedef ThreadContext::Status Status;

@@ -115,6 +117,7 @@
} floatRegs;
TheISA::IntReg intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
+ PredRegContainer predRegs[TheISA::NumPredRegs];
#ifdef ISA_HAS_CC_REGS
TheISA::CCReg ccRegs[TheISA::NumCCRegs];
#endif
@@ -234,6 +237,9 @@
for (int i = 0; i < TheISA::NumVecRegs; i++) {
vecRegs[i].zero();
}
+ for (int i = 0; i < TheISA::NumPredRegs; i++) {
+ predRegs[i].reset();
+ }
#ifdef ISA_HAS_CC_REGS
memset(ccRegs, 0, sizeof(ccRegs));
#endif
@@ -280,7 +286,7 @@
assert(flatIndex < TheISA::NumVecRegs);
const VecRegContainer& regVal = readVecRegFlat(flatIndex);
DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
- reg.index(), flatIndex,
regVal.as<TheISA::VecElem>().print());
+ reg.index(), flatIndex, regVal.print());
return regVal;
}

@@ -291,7 +297,7 @@
assert(flatIndex < TheISA::NumVecRegs);
VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
- reg.index(), flatIndex,
regVal.as<TheISA::VecElem>().print());
+ reg.index(), flatIndex, regVal.print());
return regVal;
}

@@ -364,6 +370,27 @@
return regVal;
}

+ const PredRegContainer&
+ readPredReg(const RegId& reg) const
+ {
+ int flatIndex = isa->flattenPredIndex(reg.index());
+ assert(flatIndex < TheISA::NumPredRegs);
+ const PredRegContainer& regVal = readPredRegFlat(flatIndex);
+ DPRINTF(PredRegs, "Reading predicate reg %d (%d) as %s.\n",
+ reg.index(), flatIndex, regVal.print());
+ return regVal;
+ }
+
+ PredRegContainer&
+ getWritablePredReg(const RegId& reg)
+ {
+ int flatIndex = isa->flattenPredIndex(reg.index());
+ assert(flatIndex < TheISA::NumPredRegs);
+ PredRegContainer& regVal = getWritablePredRegFlat(flatIndex);
+ DPRINTF(PredRegs, "Reading predicate reg %d (%d) as %s for
modify.\n",
+ reg.index(), flatIndex, regVal.print());
+ return regVal;
+ }

CCReg readCCReg(int reg_idx)
{
@@ -429,6 +456,15 @@
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
}

+ void setPredReg(const RegId& reg, const PredRegContainer& val)
+ {
+ int flatIndex = isa->flattenPredIndex(reg.index());
+ assert(flatIndex < TheISA::NumPredRegs);
+ setPredRegFlat(flatIndex, val);
+ DPRINTF(PredRegs, "Setting predicate reg %d (%d) to %s.\n",
+ reg.index(), flatIndex, val.print());
+ }
+
void setCCReg(int reg_idx, CCReg val)
{
#ifdef ISA_HAS_CC_REGS
@@ -584,6 +620,21 @@
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}

+ const PredRegContainer& readPredRegFlat(const RegIndex& reg) const
+ {
+ return predRegs[reg];
+ }
+
+ PredRegContainer& getWritablePredRegFlat(const RegIndex& reg)
+ {
+ return predRegs[reg];
+ }
+
+ void setPredRegFlat(const RegIndex& reg, const PredRegContainer& val)
+ {
+ predRegs[reg] = val;
+ }
+
#ifdef ISA_HAS_CC_REGS
CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 70d933c..83a50f5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -105,16 +117,17 @@
/** @{ */
int8_t _numVecDestRegs;
int8_t _numVecElemDestRegs;
+ int8_t _numPredDestRegs;
/** @} */

public:

/// @name Register information.
- /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs() and
- /// numVecelemDestRegs() equals numDestRegs(). The former two
functions
- /// are used to track physical register usage for machines with
separate
- /// int & FP reg files, the next two is for machines with vector
register
- /// file.
+ /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
+ /// numVecElemDestRegs() and numPredDestRegs() equals numDestRegs().
The
+ /// former two functions are used to track physical register usage for
+ /// machines with separate int & FP reg files, the next three are for
+ /// machines with vector and predicate register files.
//@{
/// Number of source registers.
int8_t numSrcRegs() const { return _numSrcRegs; }
@@ -128,6 +141,8 @@
int8_t numVecDestRegs() const { return _numVecDestRegs; }
/// Number of vector element destination regs.
int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
+ /// Number of predicate destination regs.
+ int8_t numPredDestRegs() const { return _numPredDestRegs; }
/// Number of coprocesor destination regs.
int8_t numCCDestRegs() const { return _numCCDestRegs; }
//@}
@@ -248,8 +263,8 @@
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass
__opClass)
: _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
_numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
- _numVecDestRegs(0), _numVecElemDestRegs(0), machInst(_machInst),
- mnemonic(_mnemonic), cachedDisassembly(0)
+ _numVecDestRegs(0), _numVecElemDestRegs(0), _numPredDestRegs(0),
+ machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
{ }

public:
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index bf25cd6..eb9cec9 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2016 ARM Limited
+ * Copyright (c) 2012, 2016-2017 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -43,6 +43,7 @@

#include "cpu/thread_context.hh"

+#include "arch/generic/pred_reg.hh"
#include "arch/kernel_stats.hh"
#include "base/logging.hh"
#include "base/trace.hh"
@@ -86,6 +87,17 @@
panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
}
+
+ // Then loop through the predicate registers.
+ for (int i = 0; i < TheISA::NumPredRegs; ++i) {
+ RegId rid(PredRegClass, i);
+ const TheISA::PredRegContainer& t1 = one->readPredReg(rid);
+ const TheISA::PredRegContainer& t2 = two->readPredReg(rid);
+ if (t1 != t2)
+ panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
+ i, t1, t2);
+ }
+
for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
@@ -168,6 +180,12 @@
}
SERIALIZE_CONTAINER(vecRegs);

+ std::vector<TheISA::PredRegContainer> predRegs(NumPredRegs);
+ for (int i = 0; i < NumPredRegs; ++i) {
+ predRegs[i] = tc.readPredRegFlat(i);
+ }
+ SERIALIZE_CONTAINER(predRegs);
+
IntReg intRegs[NumIntRegs];
for (int i = 0; i < NumIntRegs; ++i)
intRegs[i] = tc.readIntRegFlat(i);
@@ -203,6 +221,12 @@
tc.setVecRegFlat(i, vecRegs[i]);
}

+ std::vector<TheISA::PredRegContainer> predRegs(NumPredRegs);
+ UNSERIALIZE_CONTAINER(predRegs);
+ for (int i = 0; i < NumPredRegs; ++i) {
+ tc.setPredRegFlat(i, predRegs[i]);
+ }
+
IntReg intRegs[NumIntRegs];
UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
for (int i = 0; i < NumIntRegs; ++i)
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 1e30649..8e50aa8 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -102,6 +102,8 @@
typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
+ using PredRegContainer = TheISA::PredRegContainer;
+
public:

enum Status
@@ -248,6 +250,9 @@

virtual const VecElem& readVecElem(const RegId& reg) const = 0;

+ virtual const PredRegContainer& readPredReg(const RegId& reg) const =
0;
+ virtual PredRegContainer& getWritablePredReg(const RegId& reg) = 0;
+
virtual CCReg readCCReg(int reg_idx) = 0;

virtual void setIntReg(int reg_idx, uint64_t val) = 0;
@@ -260,6 +265,8 @@

virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;

+ virtual void setPredReg(const RegId& reg, const PredRegContainer& val)
= 0;
+
virtual void setCCReg(int reg_idx, CCReg val) = 0;

virtual TheISA::PCState pcState() = 0;
@@ -352,6 +359,10 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val) = 0;

+ virtual const PredRegContainer& readPredRegFlat(int idx) const = 0;
+ virtual PredRegContainer& getWritablePredRegFlat(int idx) = 0;
+ virtual void setPredRegFlat(int idx, const PredRegContainer& val) = 0;
+
virtual CCReg readCCRegFlat(int idx) = 0;
virtual void setCCRegFlat(int idx, CCReg val) = 0;
/** @} */
@@ -516,6 +527,12 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }

+ const PredRegContainer& readPredReg(const RegId& reg) const
+ { return actualTC->readPredReg(reg); }
+
+ PredRegContainer& getWritablePredReg(const RegId& reg)
+ { return actualTC->getWritablePredReg(reg); }
+
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }

@@ -531,6 +548,9 @@
void setVecReg(const RegId& reg, const VecRegContainer& val)
{ actualTC->setVecReg(reg, val); }

+ void setPredReg(const RegId& reg, const PredRegContainer& val)
+ { actualTC->setPredReg(reg, val); }
+
void setVecElem(const RegId& reg, const VecElem& val)
{ actualTC->setVecElem(reg, val); }

@@ -613,6 +633,15 @@
const VecElem& val)
{ actualTC->setVecElemFlat(id, elemIndex, val); }

+ const PredRegContainer& readPredRegFlat(int id) const
+ { return actualTC->readPredRegFlat(id); }
+
+ PredRegContainer& getWritablePredRegFlat(int id)
+ { return actualTC->getWritablePredRegFlat(id); }
+
+ void setPredRegFlat(int idx, const PredRegContainer& val)
+ { actualTC->setPredRegFlat(idx, val); }
+
CCReg readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index d57f5a0..139379a 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 ARM Limited
+ * Copyright (c) 2014, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -44,6 +44,8 @@
#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__

+#include "arch/generic/pred_reg.hh"
+#include "arch/generic/vec_reg.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
@@ -95,6 +97,9 @@
union {
uint64_t as_int;
double as_double;
+ ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
+ ::PredRegContainer<TheISA::PredRegSizeBits,
+ TheISA::PredRegHasPackedRepr>* as_pred;
} data;

/** @defgroup fetch_seq
@@ -118,7 +123,9 @@
DataInt16 = 2,
DataInt32 = 4,
DataInt64 = 8,
- DataDouble = 3
+ DataDouble = 3,
+ DataVec = 5,
+ DataPred = 6
} data_status;

/** @ingroup memory
@@ -150,7 +157,16 @@
fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
{ }

- virtual ~InstRecord() { }
+ virtual ~InstRecord()
+ {
+ if (data_status == DataVec) {
+ assert(data.as_vec);
+ delete data.as_vec;
+ } else if (data_status == DataPred) {
+ assert(data.as_pred);
+ delete data.as_pred;
+ }
+ }

void setWhen(Tick new_when) { when = new_when; }
void setMem(Addr a, Addr s, unsigned f)
@@ -181,6 +197,22 @@

void setData(double d) { data.as_double = d; data_status = DataDouble;
}

+ void
+ setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
+ {
+ data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
+ data_status = DataVec;
+ }
+
+ void
+ setData(::PredRegContainer<TheISA::PredRegSizeBits,
+ TheISA::PredRegHasPackedRepr>& d)
+ {
+ data.as_pred = new ::PredRegContainer<TheISA::PredRegSizeBits,
+
TheISA::PredRegHasPackedRepr>(d);
+ data_status = DataPred;
+ }
+
void setFetchSeq(InstSeqNum seq)
{ fetch_seq = seq; fetch_seq_valid = true; }

diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index a03a396..8c9e69b 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -57,6 +57,7 @@
#include <string>
#include <vector>

+#include "arch/generic/pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "base/framebuffer.hh"
#include "base/inifile.hh"
@@ -456,6 +457,19 @@
arrayParamIn(CheckpointIn &cp, const string &name, \
list<type> &param);

+using PredRegContainer8BitPacked = PredRegContainer< 8, true>;
+using PredRegContainer16BitPacked = PredRegContainer< 16, true>;
+using PredRegContainer32BitPacked = PredRegContainer< 32, true>;
+using PredRegContainer64BitPacked = PredRegContainer< 64, true>;
+using PredRegContainer128BitPacked = PredRegContainer<128, true>;
+using PredRegContainer256BitPacked = PredRegContainer<256, true>;
+using PredRegContainer8BitUnpacked = PredRegContainer< 8, false>;
+using PredRegContainer16BitUnpacked = PredRegContainer< 16, false>;
+using PredRegContainer32BitUnpacked = PredRegContainer< 32, false>;
+using PredRegContainer64BitUnpacked = PredRegContainer< 64, false>;
+using PredRegContainer128BitUnpacked = PredRegContainer<128, false>;
+using PredRegContainer256BitUnpacked = PredRegContainer<256, false>;
+
INSTANTIATE_PARAM_TEMPLATES(char)
INSTANTIATE_PARAM_TEMPLATES(signed char)
INSTANTIATE_PARAM_TEMPLATES(unsigned char)
@@ -474,6 +488,22 @@
INSTANTIATE_PARAM_TEMPLATES(Pixel)
INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<8>)
INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<16>)
+INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<32>)
+INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<64>)
+INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<128>)
+INSTANTIATE_PARAM_TEMPLATES(VecRegContainer<256>)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer8BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer16BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer32BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer64BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer128BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer256BitPacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer8BitUnpacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer16BitUnpacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer32BitUnpacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer64BitUnpacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer128BitUnpacked)
+INSTANTIATE_PARAM_TEMPLATES(PredRegContainer256BitUnpacked)

// set is only used with strings and furthermore doesn't agree with Pixel
template void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-MessageType: newchange
Giacomo Gabrielli (Gerrit)
2018-11-22 09:32:04 UTC
Permalink
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13715

to look at the new patch set (#4).

Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/pred_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
50 files changed, 1,290 insertions(+), 70 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13715
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Andreas Sandberg <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 09:42:45 UTC
Permalink
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13715

to look at the new patch set (#5).

Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/pred_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
49 files changed, 1,289 insertions(+), 69 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13715
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Andreas Sandberg <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 17:35:15 UTC
Permalink
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13715

to look at the new patch set (#6).

Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/pred_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
50 files changed, 1,290 insertions(+), 70 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13715
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Andreas Sandberg <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 17:38:04 UTC
Permalink
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13715

to look at the new patch set (#7).

Change subject: arch,cpu: Add vector predicate registers
......................................................................

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/isa.hh
M src/arch/arm/registers.hh
A src/arch/generic/pred_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
49 files changed, 1,289 insertions(+), 69 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13715
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Gerrit-Change-Number: 13715
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Andreas Sandberg <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
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