Discussion:
[gem5-dev] Change in gem5/gem5[master]: sim: Initialise data members
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Giacomo Gabrielli (Gerrit)
2018-10-01 08:44:13 UTC
Permalink
Giacomo Gabrielli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13125


Change subject: sim: Initialise data members
......................................................................

sim: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/tlb.cc
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
11 files changed, 68 insertions(+), 17 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 79eef1b..19a921a 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -79,7 +79,7 @@
directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
stage2Mmu(NULL), test(nullptr), rangeMRU(1),
aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
- isHyp(false), asid(0), vmid(0), dacr(0),
+ isHyp(false), asid(0), vmid(0), hcr(0), dacr(0),
miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
{
const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index b499fe4..b1ea5c3 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -63,7 +63,15 @@
const StaticInstPtr &_macroop,
TheISA::PCState _pc, TheISA::PCState
_predPC,
InstSeqNum seq_num, ImplCPU *cpu)
- : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
+ : staticInst(_staticInst), cpu(cpu),
+ thread(nullptr),
+ traceData(nullptr),
+ macroop(_macroop),
+ memData(nullptr),
+ savedReq(nullptr),
+ savedSreqLow(nullptr),
+ savedSreqHigh(nullptr),
+ reqToVerify(nullptr)
{
seqNum = seq_num;

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 8329e31..fe1c3d4 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -67,7 +67,9 @@

CheckerCPU::CheckerCPU(Params *p)
: BaseCPU(p, true), systemPtr(NULL), icachePort(NULL),
dcachePort(NULL),
- tc(NULL), thread(NULL)
+ tc(NULL), thread(NULL),
+ unverifiedReq(nullptr),
+ unverifiedMemData(nullptr)
{
curStaticInst = NULL;
curMacroStaticInst = NULL;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8fd142c..b6fcccf 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -131,17 +131,19 @@
"RoundRobin,OldestReady}");
}

- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
commitStatus[tid] = Idle;
changedROBNumEntries[tid] = false;
- checkEmptyROB[tid] = false;
- trapInFlight[tid] = false;
- committedStores[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
+ squashAfterInst[tid] = nullptr;
pc[tid].set(0);
+ youngestSeqNum[tid] = 0;
lastCommitedSeqNum[tid] = 0;
- squashAfterInst[tid] = NULL;
+ trapInFlight[tid] = false;
+ committedStores[tid] = false;
+ checkEmptyROB[tid] = false;
+ renameMap[tid] = nullptr;
}
interrupt = NoFault;
}
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 74acbd3..1d558b9 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -75,6 +75,13 @@

// @todo: Make into a parameter
skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
+ for (int tid = 0; tid < Impl::MaxThreads; tid++) {
+ stalls[tid] = {false};
+ decodeStatus[tid] = Idle;
+ bdelayDoneSeqNum[tid] = 0;
+ squashInst[tid] = nullptr;
+ squashAfterDelaySlot[tid] = 0;
+ }
}

template<class Impl>
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 28739d2..ce77ee9 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -121,7 +121,7 @@

public:
FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
- : fetch(_fetch)
+ : fetch(_fetch), req(nullptr)
{}

void setFault(Fault _fault)
@@ -138,7 +138,9 @@
void process()
{
assert(fetch->numInst < fetch->fetchWidth);
- fetch->finishTranslation(fault, req);
+ auto req_temp = req;
+ req = nullptr;
+ fetch->finishTranslation(fault, req_temp);
}

const char *description() const
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5810c03..537f930 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -80,6 +80,7 @@
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
: cpu(_cpu),
+ branchPred(nullptr),
decodeToFetchDelay(params->decodeToFetchDelay),
renameToFetchDelay(params->renameToFetchDelay),
iewToFetchDelay(params->iewToFetchDelay),
@@ -143,10 +144,19 @@
instSize = sizeof(TheISA::MachInst);

for (int i = 0; i < Impl::MaxThreads; i++) {
- decoder[i] = NULL;
+ fetchStatus[i] = Idle;
+ decoder[i] = nullptr;
+ pc[i] = 0;
+ fetchOffset[i] = 0;
+ macroop[i] = nullptr;
+ delayedCommit[i] = false;
+ memReq[i] = nullptr;
+ stalls[i] = {false, false};
fetchBuffer[i] = NULL;
fetchBufferPC[i] = 0;
fetchBufferValid[i] = false;
+ lastIcacheStall[i] = 0;
+ issuePipelinedIfetch[i] = false;
}

branchPred = params->branchPred;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index e46bc5b..e706b09 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -76,6 +76,8 @@
issueToExecuteDelay(params->issueToExecuteDelay),
dispatchWidth(params->dispatchWidth),
issueWidth(params->issueWidth),
+ wbNumInst(0),
+ wbCycle(0),
wbWidth(params->wbWidth),
numThreads(params->numThreads)
{
@@ -102,7 +104,7 @@
// Instruction queue needs the queue between issue and execute.
instQueue.setIssueToExecuteQueue(&issueToExecQueue);

- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
dispatchStatus[tid] = Running;
fetchRedirect[tid] = false;
}
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bc4822b..252afbe 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -112,7 +112,7 @@
regScoreboard.resize(numPhysRegs);

//Initialize Mem Dependence Units
- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
memDepUnit[tid].init(params, tid);
memDepUnit[tid].setIQ(this);
}
@@ -165,6 +165,9 @@
assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
}
+ for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+ maxEntries[tid] = 0;
+ }
}

template <class Impl>
@@ -406,7 +409,7 @@
InstructionQueue<Impl>::resetState()
{
//Initialize thread IQ counts
- for (ThreadID tid = 0; tid <numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
count[tid] = 0;
instList[tid].clear();
}
@@ -423,7 +426,7 @@
regScoreboard[i] = false;
}

- for (ThreadID tid = 0; tid < numThreads; ++tid) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) {
squashedSeqNum[tid] = 0;
}

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index a295a87..4331b6d 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -76,6 +76,18 @@

// @todo: Make into a parameter.
skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
+ for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
+ renameStatus[tid] = Idle;
+ renameMap[tid] = nullptr;
+ instsInProgress[tid] = 0;
+ loadsInProgress[tid] = 0;
+ storesInProgress[tid] = 0;
+ freeEntries[tid] = {0, 0, 0, 0};
+ emptyROB[tid] = true;
+ stalls[tid] = {false, false};
+ serializeInst[tid] = nullptr;
+ serializeOnNextInst[tid] = false;
+ }
}

template <class Impl>
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 223f94c..c170ec4 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -102,6 +102,9 @@
assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
}
+ for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+ maxEntries[tid] = 0;
+ }

resetState();
}
@@ -110,11 +113,11 @@
void
ROB<Impl>::resetState()
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- doneSquashing[tid] = true;
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
threadEntries[tid] = 0;
squashIt[tid] = instList[tid].end();
squashedSeqNum[tid] = 0;
+ doneSquashing[tid] = true;
}
numInstsInROB = 0;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13125
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Gerrit-Change-Number: 13125
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-MessageType: newchange
Giacomo Gabrielli (Gerrit)
2018-10-05 15:32:07 UTC
Permalink
Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13125

to look at the new patch set (#5).

Change subject: cpu,arch-arm: Initialise data members
......................................................................

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/tlb.cc
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
11 files changed, 68 insertions(+), 17 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13125
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Gerrit-Change-Number: 13125
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 09:32:04 UTC
Permalink
Hello Giacomo Travaglini, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13125

to look at the new patch set (#10).

Change subject: cpu,arch-arm: Initialise data members
......................................................................

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/tlb.cc
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
11 files changed, 66 insertions(+), 17 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13125
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Gerrit-Change-Number: 13125
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 17:35:15 UTC
Permalink
Hello Giacomo Travaglini, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13125

to look at the new patch set (#11).

Change subject: cpu,arch-arm: Initialise data members
......................................................................

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/tlb.cc
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
11 files changed, 65 insertions(+), 16 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13125
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Gerrit-Change-Number: 13125
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-28 14:12:36 UTC
Permalink
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13125 )

Change subject: cpu,arch-arm: Initialise data members
......................................................................

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <***@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <***@arm.com>
Reviewed-by: Jason Lowe-Power <***@lowepower.com>
---
M src/arch/arm/tlb.cc
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
11 files changed, 65 insertions(+), 16 deletions(-)

Approvals:
Jason Lowe-Power: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index ac18ef1..46056d0 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -79,7 +79,7 @@
directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
stage2Mmu(NULL), test(nullptr), rangeMRU(1),
aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
- isHyp(false), asid(0), vmid(0), dacr(0),
+ isHyp(false), asid(0), vmid(0), hcr(0), dacr(0),
miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
{
const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index f638f75..cd4740d 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -63,7 +63,15 @@
const StaticInstPtr &_macroop,
TheISA::PCState _pc, TheISA::PCState
_predPC,
InstSeqNum seq_num, ImplCPU *cpu)
- : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
+ : staticInst(_staticInst), cpu(cpu),
+ thread(nullptr),
+ traceData(nullptr),
+ macroop(_macroop),
+ memData(nullptr),
+ savedReq(nullptr),
+ savedSreqLow(nullptr),
+ savedSreqHigh(nullptr),
+ reqToVerify(nullptr)
{
seqNum = seq_num;

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 8329e31..fe1c3d4 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -67,7 +67,9 @@

CheckerCPU::CheckerCPU(Params *p)
: BaseCPU(p, true), systemPtr(NULL), icachePort(NULL),
dcachePort(NULL),
- tc(NULL), thread(NULL)
+ tc(NULL), thread(NULL),
+ unverifiedReq(nullptr),
+ unverifiedMemData(nullptr)
{
curStaticInst = NULL;
curMacroStaticInst = NULL;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 4775e98..40ce848 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -132,17 +132,19 @@
"RoundRobin, OldestReady");
}

- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
commitStatus[tid] = Idle;
changedROBNumEntries[tid] = false;
- checkEmptyROB[tid] = false;
- trapInFlight[tid] = false;
- committedStores[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
+ squashAfterInst[tid] = nullptr;
pc[tid].set(0);
+ youngestSeqNum[tid] = 0;
lastCommitedSeqNum[tid] = 0;
- squashAfterInst[tid] = NULL;
+ trapInFlight[tid] = false;
+ committedStores[tid] = false;
+ checkEmptyROB[tid] = false;
+ renameMap[tid] = nullptr;
}
interrupt = NoFault;
}
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 51c1b9d..63b180e 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -75,6 +75,13 @@

// @todo: Make into a parameter
skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth;
+ for (int tid = 0; tid < Impl::MaxThreads; tid++) {
+ stalls[tid] = {false};
+ decodeStatus[tid] = Idle;
+ bdelayDoneSeqNum[tid] = 0;
+ squashInst[tid] = nullptr;
+ squashAfterDelaySlot[tid] = 0;
+ }
}

template<class Impl>
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 28739d2..ce4f8b6 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -121,7 +121,7 @@

public:
FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
- : fetch(_fetch)
+ : fetch(_fetch), req(nullptr)
{}

void setFault(Fault _fault)
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5810c03..537f930 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -80,6 +80,7 @@
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
: cpu(_cpu),
+ branchPred(nullptr),
decodeToFetchDelay(params->decodeToFetchDelay),
renameToFetchDelay(params->renameToFetchDelay),
iewToFetchDelay(params->iewToFetchDelay),
@@ -143,10 +144,19 @@
instSize = sizeof(TheISA::MachInst);

for (int i = 0; i < Impl::MaxThreads; i++) {
- decoder[i] = NULL;
+ fetchStatus[i] = Idle;
+ decoder[i] = nullptr;
+ pc[i] = 0;
+ fetchOffset[i] = 0;
+ macroop[i] = nullptr;
+ delayedCommit[i] = false;
+ memReq[i] = nullptr;
+ stalls[i] = {false, false};
fetchBuffer[i] = NULL;
fetchBufferPC[i] = 0;
fetchBufferValid[i] = false;
+ lastIcacheStall[i] = 0;
+ issuePipelinedIfetch[i] = false;
}

branchPred = params->branchPred;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index e46bc5b..e706b09 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -76,6 +76,8 @@
issueToExecuteDelay(params->issueToExecuteDelay),
dispatchWidth(params->dispatchWidth),
issueWidth(params->issueWidth),
+ wbNumInst(0),
+ wbCycle(0),
wbWidth(params->wbWidth),
numThreads(params->numThreads)
{
@@ -102,7 +104,7 @@
// Instruction queue needs the queue between issue and execute.
instQueue.setIssueToExecuteQueue(&issueToExecQueue);

- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
dispatchStatus[tid] = Running;
fetchRedirect[tid] = false;
}
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 410c15f..b34e6d9 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -113,7 +113,7 @@
regScoreboard.resize(numPhysRegs);

//Initialize Mem Dependence Units
- for (ThreadID tid = 0; tid < numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
memDepUnit[tid].init(params, tid);
memDepUnit[tid].setIQ(this);
}
@@ -166,6 +166,9 @@
panic("Invalid IQ sharing policy. Options are: Dynamic, "
"Partitioned, Threshold");
}
+ for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+ maxEntries[tid] = 0;
+ }
}

template <class Impl>
@@ -407,7 +410,7 @@
InstructionQueue<Impl>::resetState()
{
//Initialize thread IQ counts
- for (ThreadID tid = 0; tid <numThreads; tid++) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
count[tid] = 0;
instList[tid].clear();
}
@@ -424,7 +427,7 @@
regScoreboard[i] = false;
}

- for (ThreadID tid = 0; tid < numThreads; ++tid) {
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) {
squashedSeqNum[tid] = 0;
}

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index a295a87..4331b6d 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -76,6 +76,18 @@

// @todo: Make into a parameter.
skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
+ for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
+ renameStatus[tid] = Idle;
+ renameMap[tid] = nullptr;
+ instsInProgress[tid] = 0;
+ loadsInProgress[tid] = 0;
+ storesInProgress[tid] = 0;
+ freeEntries[tid] = {0, 0, 0, 0};
+ emptyROB[tid] = true;
+ stalls[tid] = {false, false};
+ serializeInst[tid] = nullptr;
+ serializeOnNextInst[tid] = false;
+ }
}

template <class Impl>
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 991dc96..3a0140b 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -103,6 +103,9 @@
panic("Invalid ROB sharing policy. Options are: Dynamic, "
"Partitioned, Threshold");
}
+ for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
+ maxEntries[tid] = 0;
+ }

resetState();
}
@@ -111,11 +114,11 @@
void
ROB<Impl>::resetState()
{
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- doneSquashing[tid] = true;
+ for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
threadEntries[tid] = 0;
squashIt[tid] = instList[tid].end();
squashedSeqNum[tid] = 0;
+ doneSquashing[tid] = true;
}
numInstsInROB = 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Gerrit-Change-Number: 13125
Gerrit-PatchSet: 13
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-CC: Brandon Potter <***@amd.com>
Gerrit-MessageType: merged
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