Discussion:
[gem5-dev] Change in gem5/gem5[master]: arch, base, cpu, gpu,
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Gabe Black (Gerrit)
2018-11-27 01:55:31 UTC
Permalink
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14636


Change subject: arch, base, cpu, gpu, mem: Replace assert(0 or false with
panic.
......................................................................

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
---
M src/arch/arm/insts/fplib.cc
M src/arch/arm/insts/pred_inst.hh
M src/arch/mips/isa/formats/mem.isa
M src/base/inet.cc
M src/cpu/minor/buffers.hh
M src/cpu/minor/lsq.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/rob_impl.hh
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
M src/mem/cache/queue.hh
M src/mem/mem_checker_monitor.cc
M src/mem/ruby/filters/H3BloomFilter.cc
M src/mem/ruby/filters/MultiBitSelBloomFilter.cc
M src/mem/ruby/network/garnet2.0/RoutingUnit.cc
M src/mem/ruby/structures/CacheMemory.cc
20 files changed, 68 insertions(+), 63 deletions(-)



diff --git a/src/arch/arm/insts/fplib.cc b/src/arch/arm/insts/fplib.cc
index 8ef1277..49305ec 100644
--- a/src/arch/arm/insts/fplib.cc
+++ b/src/arch/arm/insts/fplib.cc
@@ -42,6 +42,7 @@

#include <cassert>

+#include "base/logging.hh"
#include "fplib.hh"

namespace ArmISA
@@ -3740,7 +3741,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp16_infinity(sgn) :
fp16_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3802,7 +3803,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp32_infinity(sgn) :
fp32_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3864,7 +3865,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp64_infinity(sgn) :
fp64_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -4108,7 +4109,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4173,7 +4174,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4238,7 +4239,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4575,7 +4576,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (u ? sgn && x : x > (1ULL << (FP64_BITS - 1)) - !sgn) {
diff --git a/src/arch/arm/insts/pred_inst.hh
b/src/arch/arm/insts/pred_inst.hh
index 62d1c09..38ff8ad 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -43,6 +43,7 @@
#define __ARCH_ARM_INSTS_PREDINST_HH__

#include "arch/arm/insts/static_inst.hh"
+#include "base/logging.hh"
#include "base/trace.hh"

namespace ArmISA
@@ -186,7 +187,7 @@
(bits(bigData, 7) << 63);
break;
default:
- assert(0);
+ panic("Unrecognized FP data type");
}
return bigData;
}
diff --git a/src/arch/mips/isa/formats/mem.isa
b/src/arch/mips/isa/formats/mem.isa
index a2710fb..e2204db 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -121,9 +121,7 @@
return packet->getLE<uint64_t>();

default:
- std::cerr << "bad store data size = " << packet->getSize() <<
std::endl;
-
- assert(0);
+ panic("bad store data size = %d", packet->getSize());
return 0;
}
}
diff --git a/src/base/inet.cc b/src/base/inet.cc
index 57af0e5..44a37d2 100644
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -51,6 +51,7 @@
#include <string>

#include "base/cprintf.hh"
+#include "base/logging.hh"
#include "base/types.hh"

using namespace std;
@@ -238,7 +239,7 @@
} else if (Ip6Ptr(tcp.packet())) {
return __tu_cksum6(Ip6Ptr(tcp.packet()));
} else {
- assert(0);
+ panic("Unrecognized IP packet format");
}
// Should never reach here
return 0;
@@ -252,7 +253,7 @@
} else if (Ip6Ptr(udp.packet())) {
return __tu_cksum6(Ip6Ptr(udp.packet()));
} else {
- assert(0);
+ panic("Unrecognized IP packet format");
}
return 0;
}
diff --git a/src/cpu/minor/buffers.hh b/src/cpu/minor/buffers.hh
index 864b29e..edf87de 100644
--- a/src/cpu/minor/buffers.hh
+++ b/src/cpu/minor/buffers.hh
@@ -118,7 +118,11 @@
{
public:
static bool isBubble(const ElemType &) { return false; }
- static ElemType bubble() { assert(false); }
+ static ElemType
+ bubble()
+ {
+ panic("bubble called but no bubble interface");
+ }
};

/** Pass on call to the element */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index ad103b0..b836ed2 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -44,6 +44,7 @@

#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
+#include "base/logging.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
#include "cpu/minor/execute.hh"
@@ -1121,8 +1122,7 @@
request->setState(LSQRequest::StoreBufferIssuing);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized LSQ request state %d.",
request->state);
}

state = MemoryRunning;
@@ -1144,8 +1144,7 @@
request->setState(LSQRequest::StoreBufferNeedsRetry);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized LSQ request state %d.",
request->state);
}
}
}
@@ -1226,10 +1225,7 @@
}
break;
default:
- /* Shouldn't be allowed to receive a response from another
- * state */
- assert(false);
- break;
+ panic("Shouldn't be allowed to receive a response from another
state");
}

/* We go to idle even if there are more things in the requests queue
@@ -1260,7 +1256,7 @@
retryRequest->setState(LSQRequest::StoreInStoreBuffer);
break;
default:
- assert(false);
+ panic("Unrecognized retry request state %d.", retryRequest->state);
}

/* Set state back to MemoryRunning so that the following
@@ -1283,8 +1279,7 @@
storeBuffer.countIssuedStore(retryRequest);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized retry request state %d.",
retryRequest->state);
}

retryRequest = NULL;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8fd142c..4775e98 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -49,8 +49,9 @@
#include <string>

#include "arch/utility.hh"
-#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
+#include "base/loader/symtab.hh"
+#include "base/logging.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/o3/commit.hh"
@@ -127,8 +128,8 @@

DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
} else {
- assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
- "RoundRobin,OldestReady}");
+ panic("Invalid SMT commit policy. Options are: Aggressive, "
+ "RoundRobin, OldestReady");
}

for (ThreadID tid = 0; tid < numThreads; tid++) {
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bc4822b..410c15f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -48,6 +48,7 @@
#include <limits>
#include <vector>

+#include "base/logging.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include "debug/IQ.hh"
@@ -162,8 +163,8 @@
DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
} else {
- assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid IQ sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}
}

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 967a496..83de8dd 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -48,6 +48,7 @@
#include <list>
#include <string>

+#include "base/logging.hh"
#include "cpu/o3/lsq.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
@@ -109,8 +110,8 @@
"%i entries per LQ | %i entries per SQ\n",
maxLQEntries,maxSQEntries);
} else {
- assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid LSQ sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}

//Initialize LSQs
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 223f94c..991dc96 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -46,6 +46,7 @@

#include <list>

+#include "base/logging.hh"
#include "cpu/o3/rob.hh"
#include "debug/Fetch.hh"
#include "debug/ROB.hh"
@@ -99,8 +100,8 @@
maxEntries[tid] = threshold;
}
} else {
- assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid ROB sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}

resetState();
diff --git a/src/gpu-compute/gpu_dyn_inst.hh
b/src/gpu-compute/gpu_dyn_inst.hh
index 0d357de..9e63c44 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -39,6 +39,7 @@
#include <cstdint>
#include <string>

+#include "base/logging.hh"
#include "enums/MemType.hh"
#include "enums/StorageClassType.hh"
#include "gpu-compute/compute_unit.hh"
@@ -407,8 +408,7 @@
} else if (isGroupSeg()) {
req->setMemSpaceConfigFlags(Request::GROUP_SEGMENT);
} else if (isFlat()) {
- // TODO: translate to correct scope
- assert(false);
+ panic("TODO: translate to correct scope");
} else {
fatal("%s has bad segment type\n", disassemble());
}
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index fea6183..dbf7d26 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -45,6 +45,7 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
+#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
@@ -1150,16 +1151,16 @@

if ((inUser && !tlb_entry->user) ||
(mode == BaseTLB::Write && badWrite)) {
- // The page must have been present to get into the TLB in
- // the first place. We'll assume the reserved bits are
- // fine even though we're not checking them.
- assert(false);
+ // The page must have been present to get into the TLB in
+ // the first place. We'll assume the reserved bits are
+ // fine even though we're not checking them.
+ panic("Page fault detected");
}

if (storeCheck && badWrite) {
- // This would fault if this were a write, so return a page
- // fault that reflects that happening.
- assert(false);
+ // This would fault if this were a write, so return a page
+ // fault that reflects that happening.
+ panic("Page fault detected");
}
}

@@ -1362,7 +1363,7 @@
*/
handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
} else {
- assert(false);
+ panic("Unexpected TLB outcome %d", outcome);
}
}

@@ -1607,7 +1608,7 @@
{
// The CPUSidePort never sends anything but replies. No retries
// expected.
- assert(false);
+ panic("recvReqRetry called");
}

AddrRangeList
@@ -1648,7 +1649,7 @@
{
// No retries should reach the TLB. The retries
// should only reach the TLBCoalescer.
- assert(false);
+ panic("recvReqRetry called");
}

void
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 04d9bfc..9ca478d 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -272,7 +272,7 @@
virtual void recvFunctional(PacketPtr pkt);
virtual void recvRangeChange() { }
virtual void recvReqRetry();
- virtual void recvRespRetry() { assert(false); }
+ virtual void recvRespRetry() { panic("recvRespRetry called"); }
virtual AddrRangeList getAddrRanges() const;
};

diff --git a/src/gpu-compute/tlb_coalescer.cc
b/src/gpu-compute/tlb_coalescer.cc
index 68d2689..193c44e 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -37,6 +37,7 @@

#include <cstring>

+#include "base/logging.hh"
#include "debug/GPUTLB.hh"
#include "sim/process.hh"

@@ -335,7 +336,7 @@
void
TLBCoalescer::CpuSidePort::recvReqRetry()
{
- assert(false);
+ panic("recvReqRetry called");
}

void
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index 1d7ce0c..36ddb96 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -52,6 +52,7 @@
#include <cassert>
#include <string>

+#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Drain.hh"
@@ -108,8 +109,7 @@
return readyList.insert(i, entry);
}
}
- assert(false);
- return readyList.end(); // keep stupid compilers happy
+ panic("Failed to add to ready list.");
}

/** The number of entries that are in service. */
diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc
index ee7eb3f..75c797c 100644
--- a/src/mem/mem_checker_monitor.cc
+++ b/src/mem/mem_checker_monitor.cc
@@ -43,6 +43,7 @@

#include <memory>

+#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
@@ -129,15 +130,13 @@
Tick
MemCheckerMonitor::recvAtomic(PacketPtr pkt)
{
- assert(false && "Atomic not supported");
- return masterPort.sendAtomic(pkt);
+ panic("Atomic not supported");
}

Tick
MemCheckerMonitor::recvAtomicSnoop(PacketPtr pkt)
{
- assert(false && "Atomic not supported");
- return slavePort.sendAtomicSnoop(pkt);
+ panic("Atomic not supported");
}

bool
diff --git a/src/mem/ruby/filters/H3BloomFilter.cc
b/src/mem/ruby/filters/H3BloomFilter.cc
index 10dc4d2..71d4c88 100644
--- a/src/mem/ruby/filters/H3BloomFilter.cc
+++ b/src/mem/ruby/filters/H3BloomFilter.cc
@@ -29,6 +29,7 @@
#include "mem/ruby/filters/H3BloomFilter.hh"

#include "base/intmath.hh"
+#include "base/logging.hh"

using namespace std;

@@ -437,8 +438,7 @@
void
H3BloomFilter::unset(Addr addr)
{
- cout << "ERROR: Unset should never be called in a Bloom filter";
- assert(0);
+ panic("ERROR: Unset should never be called in a Bloom filter");
}

bool
diff --git a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
index 5faaa10..e2ca4d0 100644
--- a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
+++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
@@ -31,6 +31,7 @@
#include <vector>

#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/str.hh"

using namespace std;
@@ -111,8 +112,7 @@
void
MultiBitSelBloomFilter::unset(Addr addr)
{
- cout << "ERROR: Unset should never be called in a Bloom filter";
- assert(0);
+ panic("ERROR: Unset should never be called in a Bloom filter");
}

bool
diff --git a/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
b/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
index 695f50e..b39bb3c 100644
--- a/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
@@ -34,6 +34,7 @@
#include "mem/ruby/network/garnet2.0/RoutingUnit.hh"

#include "base/cast.hh"
+#include "base/logging.hh"
#include "mem/ruby/network/garnet2.0/InputUnit.hh"
#include "mem/ruby/network/garnet2.0/Router.hh"
#include "mem/ruby/slicc_interface/Message.hh"
@@ -224,7 +225,7 @@
// x_hops == 0 and y_hops == 0
// this is not possible
// already checked that in outportCompute() function
- assert(0);
+ panic("x_hops == y_hops == 0");
}

return m_outports_dirn2idx[outport_dirn];
@@ -237,6 +238,5 @@
int inport,
PortDirection inport_dirn)
{
- assert(0);
- return -1;
+ panic("%s placeholder executed", __FUNCTION__);
}
diff --git a/src/mem/ruby/structures/CacheMemory.cc
b/src/mem/ruby/structures/CacheMemory.cc
index 8d99c90..6c93c32 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -30,6 +30,7 @@
#include "mem/ruby/structures/CacheMemory.hh"

#include "base/intmath.hh"
+#include "base/logging.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyCacheTrace.hh"
#include "debug/RubyResourceStalls.hh"
@@ -637,8 +638,7 @@
return false;
}
} else {
- assert(false);
- return true;
+ panic("Unrecognized cache resource type.");
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14636
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Gerrit-Change-Number: 14636
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-MessageType: newchange
Gabe Black (Gerrit)
2018-11-27 21:58:27 UTC
Permalink
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14636 )

Change subject: arch, base, cpu, gpu, mem: Replace assert(0 or false with
panic.
......................................................................

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <***@amd.com>
Reviewed-by: Jason Lowe-Power <***@lowepower.com>
Maintainer: Jason Lowe-Power <***@lowepower.com>
---
M src/arch/arm/insts/fplib.cc
M src/arch/arm/insts/pred_inst.hh
M src/arch/mips/isa/formats/mem.isa
M src/base/inet.cc
M src/cpu/minor/buffers.hh
M src/cpu/minor/lsq.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/rob_impl.hh
M src/gpu-compute/gpu_dyn_inst.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
M src/mem/cache/queue.hh
M src/mem/mem_checker_monitor.cc
M src/mem/ruby/filters/H3BloomFilter.cc
M src/mem/ruby/filters/MultiBitSelBloomFilter.cc
M src/mem/ruby/network/garnet2.0/RoutingUnit.cc
M src/mem/ruby/structures/CacheMemory.cc
20 files changed, 68 insertions(+), 63 deletions(-)

Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved



diff --git a/src/arch/arm/insts/fplib.cc b/src/arch/arm/insts/fplib.cc
index 8ef1277..49305ec 100644
--- a/src/arch/arm/insts/fplib.cc
+++ b/src/arch/arm/insts/fplib.cc
@@ -42,6 +42,7 @@

#include <cassert>

+#include "base/logging.hh"
#include "fplib.hh"

namespace ArmISA
@@ -3740,7 +3741,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp16_infinity(sgn) :
fp16_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3802,7 +3803,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp32_infinity(sgn) :
fp32_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -3864,7 +3865,7 @@
overflow_to_inf = false;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}
result = overflow_to_inf ? fp64_infinity(sgn) :
fp64_max_normal(sgn);
flags |= FPLIB_OFC | FPLIB_IXC;
@@ -4108,7 +4109,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4173,7 +4174,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4238,7 +4239,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (x == 0) {
@@ -4575,7 +4576,7 @@
x += err >> 1;
break;
default:
- assert(0);
+ panic("Unrecognized FP rounding mode");
}

if (u ? sgn && x : x > (1ULL << (FP64_BITS - 1)) - !sgn) {
diff --git a/src/arch/arm/insts/pred_inst.hh
b/src/arch/arm/insts/pred_inst.hh
index 62d1c09..38ff8ad 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -43,6 +43,7 @@
#define __ARCH_ARM_INSTS_PREDINST_HH__

#include "arch/arm/insts/static_inst.hh"
+#include "base/logging.hh"
#include "base/trace.hh"

namespace ArmISA
@@ -186,7 +187,7 @@
(bits(bigData, 7) << 63);
break;
default:
- assert(0);
+ panic("Unrecognized FP data type");
}
return bigData;
}
diff --git a/src/arch/mips/isa/formats/mem.isa
b/src/arch/mips/isa/formats/mem.isa
index a2710fb..e2204db 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -121,9 +121,7 @@
return packet->getLE<uint64_t>();

default:
- std::cerr << "bad store data size = " << packet->getSize() <<
std::endl;
-
- assert(0);
+ panic("bad store data size = %d", packet->getSize());
return 0;
}
}
diff --git a/src/base/inet.cc b/src/base/inet.cc
index 57af0e5..44a37d2 100644
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -51,6 +51,7 @@
#include <string>

#include "base/cprintf.hh"
+#include "base/logging.hh"
#include "base/types.hh"

using namespace std;
@@ -238,7 +239,7 @@
} else if (Ip6Ptr(tcp.packet())) {
return __tu_cksum6(Ip6Ptr(tcp.packet()));
} else {
- assert(0);
+ panic("Unrecognized IP packet format");
}
// Should never reach here
return 0;
@@ -252,7 +253,7 @@
} else if (Ip6Ptr(udp.packet())) {
return __tu_cksum6(Ip6Ptr(udp.packet()));
} else {
- assert(0);
+ panic("Unrecognized IP packet format");
}
return 0;
}
diff --git a/src/cpu/minor/buffers.hh b/src/cpu/minor/buffers.hh
index 864b29e..edf87de 100644
--- a/src/cpu/minor/buffers.hh
+++ b/src/cpu/minor/buffers.hh
@@ -118,7 +118,11 @@
{
public:
static bool isBubble(const ElemType &) { return false; }
- static ElemType bubble() { assert(false); }
+ static ElemType
+ bubble()
+ {
+ panic("bubble called but no bubble interface");
+ }
};

/** Pass on call to the element */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index ad103b0..b836ed2 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -44,6 +44,7 @@

#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
+#include "base/logging.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/exec_context.hh"
#include "cpu/minor/execute.hh"
@@ -1121,8 +1122,7 @@
request->setState(LSQRequest::StoreBufferIssuing);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized LSQ request state %d.",
request->state);
}

state = MemoryRunning;
@@ -1144,8 +1144,7 @@
request->setState(LSQRequest::StoreBufferNeedsRetry);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized LSQ request state %d.",
request->state);
}
}
}
@@ -1226,10 +1225,7 @@
}
break;
default:
- /* Shouldn't be allowed to receive a response from another
- * state */
- assert(false);
- break;
+ panic("Shouldn't be allowed to receive a response from another
state");
}

/* We go to idle even if there are more things in the requests queue
@@ -1260,7 +1256,7 @@
retryRequest->setState(LSQRequest::StoreInStoreBuffer);
break;
default:
- assert(false);
+ panic("Unrecognized retry request state %d.", retryRequest->state);
}

/* Set state back to MemoryRunning so that the following
@@ -1283,8 +1279,7 @@
storeBuffer.countIssuedStore(retryRequest);
break;
default:
- assert(false);
- break;
+ panic("Unrecognized retry request state %d.",
retryRequest->state);
}

retryRequest = NULL;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8fd142c..4775e98 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -49,8 +49,9 @@
#include <string>

#include "arch/utility.hh"
-#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
+#include "base/loader/symtab.hh"
+#include "base/logging.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/o3/commit.hh"
@@ -127,8 +128,8 @@

DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
} else {
- assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
- "RoundRobin,OldestReady}");
+ panic("Invalid SMT commit policy. Options are: Aggressive, "
+ "RoundRobin, OldestReady");
}

for (ThreadID tid = 0; tid < numThreads; tid++) {
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bc4822b..410c15f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -48,6 +48,7 @@
#include <limits>
#include <vector>

+#include "base/logging.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include "debug/IQ.hh"
@@ -162,8 +163,8 @@
DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
} else {
- assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid IQ sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}
}

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 967a496..83de8dd 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -48,6 +48,7 @@
#include <list>
#include <string>

+#include "base/logging.hh"
#include "cpu/o3/lsq.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
@@ -109,8 +110,8 @@
"%i entries per LQ | %i entries per SQ\n",
maxLQEntries,maxSQEntries);
} else {
- assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid LSQ sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}

//Initialize LSQs
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 223f94c..991dc96 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -46,6 +46,7 @@

#include <list>

+#include "base/logging.hh"
#include "cpu/o3/rob.hh"
#include "debug/Fetch.hh"
#include "debug/ROB.hh"
@@ -99,8 +100,8 @@
maxEntries[tid] = threshold;
}
} else {
- assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
- "Partitioned, Threshold}");
+ panic("Invalid ROB sharing policy. Options are: Dynamic, "
+ "Partitioned, Threshold");
}

resetState();
diff --git a/src/gpu-compute/gpu_dyn_inst.hh
b/src/gpu-compute/gpu_dyn_inst.hh
index 0d357de..9e63c44 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -39,6 +39,7 @@
#include <cstdint>
#include <string>

+#include "base/logging.hh"
#include "enums/MemType.hh"
#include "enums/StorageClassType.hh"
#include "gpu-compute/compute_unit.hh"
@@ -407,8 +408,7 @@
} else if (isGroupSeg()) {
req->setMemSpaceConfigFlags(Request::GROUP_SEGMENT);
} else if (isFlat()) {
- // TODO: translate to correct scope
- assert(false);
+ panic("TODO: translate to correct scope");
} else {
fatal("%s has bad segment type\n", disassemble());
}
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index fea6183..dbf7d26 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -45,6 +45,7 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
+#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
@@ -1150,16 +1151,16 @@

if ((inUser && !tlb_entry->user) ||
(mode == BaseTLB::Write && badWrite)) {
- // The page must have been present to get into the TLB in
- // the first place. We'll assume the reserved bits are
- // fine even though we're not checking them.
- assert(false);
+ // The page must have been present to get into the TLB in
+ // the first place. We'll assume the reserved bits are
+ // fine even though we're not checking them.
+ panic("Page fault detected");
}

if (storeCheck && badWrite) {
- // This would fault if this were a write, so return a page
- // fault that reflects that happening.
- assert(false);
+ // This would fault if this were a write, so return a page
+ // fault that reflects that happening.
+ panic("Page fault detected");
}
}

@@ -1362,7 +1363,7 @@
*/
handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
} else {
- assert(false);
+ panic("Unexpected TLB outcome %d", outcome);
}
}

@@ -1607,7 +1608,7 @@
{
// The CPUSidePort never sends anything but replies. No retries
// expected.
- assert(false);
+ panic("recvReqRetry called");
}

AddrRangeList
@@ -1648,7 +1649,7 @@
{
// No retries should reach the TLB. The retries
// should only reach the TLBCoalescer.
- assert(false);
+ panic("recvReqRetry called");
}

void
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 04d9bfc..9ca478d 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -272,7 +272,7 @@
virtual void recvFunctional(PacketPtr pkt);
virtual void recvRangeChange() { }
virtual void recvReqRetry();
- virtual void recvRespRetry() { assert(false); }
+ virtual void recvRespRetry() { panic("recvRespRetry called"); }
virtual AddrRangeList getAddrRanges() const;
};

diff --git a/src/gpu-compute/tlb_coalescer.cc
b/src/gpu-compute/tlb_coalescer.cc
index 68d2689..193c44e 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -37,6 +37,7 @@

#include <cstring>

+#include "base/logging.hh"
#include "debug/GPUTLB.hh"
#include "sim/process.hh"

@@ -335,7 +336,7 @@
void
TLBCoalescer::CpuSidePort::recvReqRetry()
{
- assert(false);
+ panic("recvReqRetry called");
}

void
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index 1d7ce0c..36ddb96 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -52,6 +52,7 @@
#include <cassert>
#include <string>

+#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Drain.hh"
@@ -108,8 +109,7 @@
return readyList.insert(i, entry);
}
}
- assert(false);
- return readyList.end(); // keep stupid compilers happy
+ panic("Failed to add to ready list.");
}

/** The number of entries that are in service. */
diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc
index ee7eb3f..75c797c 100644
--- a/src/mem/mem_checker_monitor.cc
+++ b/src/mem/mem_checker_monitor.cc
@@ -43,6 +43,7 @@

#include <memory>

+#include "base/logging.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
@@ -129,15 +130,13 @@
Tick
MemCheckerMonitor::recvAtomic(PacketPtr pkt)
{
- assert(false && "Atomic not supported");
- return masterPort.sendAtomic(pkt);
+ panic("Atomic not supported");
}

Tick
MemCheckerMonitor::recvAtomicSnoop(PacketPtr pkt)
{
- assert(false && "Atomic not supported");
- return slavePort.sendAtomicSnoop(pkt);
+ panic("Atomic not supported");
}

bool
diff --git a/src/mem/ruby/filters/H3BloomFilter.cc
b/src/mem/ruby/filters/H3BloomFilter.cc
index 10dc4d2..71d4c88 100644
--- a/src/mem/ruby/filters/H3BloomFilter.cc
+++ b/src/mem/ruby/filters/H3BloomFilter.cc
@@ -29,6 +29,7 @@
#include "mem/ruby/filters/H3BloomFilter.hh"

#include "base/intmath.hh"
+#include "base/logging.hh"

using namespace std;

@@ -437,8 +438,7 @@
void
H3BloomFilter::unset(Addr addr)
{
- cout << "ERROR: Unset should never be called in a Bloom filter";
- assert(0);
+ panic("ERROR: Unset should never be called in a Bloom filter");
}

bool
diff --git a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
index 5faaa10..e2ca4d0 100644
--- a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
+++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
@@ -31,6 +31,7 @@
#include <vector>

#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/str.hh"

using namespace std;
@@ -111,8 +112,7 @@
void
MultiBitSelBloomFilter::unset(Addr addr)
{
- cout << "ERROR: Unset should never be called in a Bloom filter";
- assert(0);
+ panic("ERROR: Unset should never be called in a Bloom filter");
}

bool
diff --git a/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
b/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
index 695f50e..b39bb3c 100644
--- a/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
@@ -34,6 +34,7 @@
#include "mem/ruby/network/garnet2.0/RoutingUnit.hh"

#include "base/cast.hh"
+#include "base/logging.hh"
#include "mem/ruby/network/garnet2.0/InputUnit.hh"
#include "mem/ruby/network/garnet2.0/Router.hh"
#include "mem/ruby/slicc_interface/Message.hh"
@@ -224,7 +225,7 @@
// x_hops == 0 and y_hops == 0
// this is not possible
// already checked that in outportCompute() function
- assert(0);
+ panic("x_hops == y_hops == 0");
}

return m_outports_dirn2idx[outport_dirn];
@@ -237,6 +238,5 @@
int inport,
PortDirection inport_dirn)
{
- assert(0);
- return -1;
+ panic("%s placeholder executed", __FUNCTION__);
}
diff --git a/src/mem/ruby/structures/CacheMemory.cc
b/src/mem/ruby/structures/CacheMemory.cc
index 8d99c90..6c93c32 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -30,6 +30,7 @@
#include "mem/ruby/structures/CacheMemory.hh"

#include "base/intmath.hh"
+#include "base/logging.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyCacheTrace.hh"
#include "debug/RubyResourceStalls.hh"
@@ -637,8 +638,7 @@
return false;
}
} else {
- assert(false);
- return true;
+ panic("Unrecognized cache resource type.");
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Gerrit-Change-Number: 14636
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Brandon Potter <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-MessageType: merged
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