Discussion:
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for the Scalable Vector Extension
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Giacomo Gabrielli (Gerrit)
2018-10-15 16:09:31 UTC
Permalink
Giacomo Gabrielli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13515


Change subject: arch-arm: Add initial support for the Scalable Vector
Extension
......................................................................

arch-arm: Add initial support for the Scalable Vector Extension

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- an additional predicate register file;
- basic system-level support.

Additional authors:
- Javier Setoain <***@arm.com>
- Gabor Dozsa <***@arm.com>
- Giacomo Travaglini <***@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/fs.py
M configs/example/se.py
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
A src/arch/generic/pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/FuncUnit.py
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/exetrace.cc
M src/cpu/inst_res.hh
M src/cpu/minor/MinorCPU.py
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/op_class.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
98 files changed, 12,528 insertions(+), 129 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-MessageType: newchange
Giacomo Travaglini (Gerrit)
2018-10-19 16:06:37 UTC
Permalink
Giacomo Travaglini has uploaded a new patch set (#4) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13515 )

Change subject: arch-arm: Add initial support for the Scalable Vector
Extension
......................................................................

arch-arm: Add initial support for the Scalable Vector Extension

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- an additional predicate register file;
- basic system-level support.

Additional authors:
- Javier Setoain <***@arm.com>
- Gabor Dozsa <***@arm.com>
- Giacomo Travaglini <***@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/fs.py
M configs/example/se.py
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
A src/arch/generic/pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/FuncUnit.py
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/exetrace.cc
M src/cpu/inst_res.hh
M src/cpu/minor/MinorCPU.py
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/op_class.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
98 files changed, 12,528 insertions(+), 129 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-10-23 09:48:36 UTC
Permalink
Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13515

to look at the new patch set (#5).

Change subject: arch-arm,cpu: Add initial support for Arm SVE
......................................................................

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <***@arm.com>
- Gabor Dozsa <***@arm.com>
- Giacomo Travaglini <***@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/vec_reg.hh
M src/cpu/FuncUnit.py
M src/cpu/checker/thread_context.hh
M src/cpu/exetrace.cc
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/thread_context.hh
M src/cpu/op_class.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
49 files changed, 11,193 insertions(+), 59 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-MessageType: newpatchset
Giacomo Gabrielli (Gerrit)
2018-11-22 17:35:15 UTC
Permalink
Hello Giacomo Travaglini,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13515

to look at the new patch set (#8).

Change subject: arch-arm,cpu: Add initial support for Arm SVE
......................................................................

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <***@arm.com>
- Gabor Dozsa <***@arm.com>
- Giacomo Travaglini <***@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <***@arm.com>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/vec_reg.hh
M src/cpu/FuncUnit.py
M src/cpu/checker/thread_context.hh
M src/cpu/exetrace.cc
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/thread_context.hh
M src/cpu/op_class.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
49 files changed, 11,205 insertions(+), 58 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 8
Gerrit-Owner: Giacomo Gabrielli <***@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <***@arm.com>
Gerrit-MessageType: newpatchset
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