Discussion:
[gem5-dev] Change in gem5/gem5[master]: cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
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Gabe Black (Gerrit)
2018-10-19 00:59:23 UTC
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Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13624


Change subject: cpu: dev: sim: gpu-compute: Banish some ISA specific
register types.
......................................................................

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_tlb.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_emul.hh
25 files changed, 546 insertions(+), 444 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 93cafd6..70b8f9e 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -649,7 +649,7 @@
/** @} */

/** Records an integer register being set to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
@@ -661,7 +661,7 @@
}

/** Records an fp register being set to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatRegVal val)
{
setScalarResult(val);
}
@@ -675,7 +675,7 @@

/** Records an fp register being set to an integer value. */
void
- setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index bee7225..21bd4fd 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -88,9 +88,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;

/** id attached to all issued requests */
@@ -189,22 +186,24 @@
// storage (which is pretty hard to imagine they would have reason
// to do).

- IntReg readIntRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isIntReg());
return thread->readIntReg(reg.index());
}

- FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
+ FloatRegVal
+ readFloatRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
return thread->readFloatReg(reg.index());
}

- FloatRegBits readFloatRegOperandBits(const StaticInst *si,
- int idx) override
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
@@ -214,8 +213,8 @@
/**
* Read source vector register operand.
*/
- const VecRegContainer& readVecRegOperand(const StaticInst *si,
- int idx) const override
+ const VecRegContainer &
+ readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
@@ -225,8 +224,8 @@
/**
* Read destination vector register operand for modification.
*/
- VecRegContainer& getWritableVecRegOperand(const StaticInst *si,
- int idx) override
+ VecRegContainer &
+ getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -237,8 +236,7 @@
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
- readVec8BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec8BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -247,8 +245,7 @@

/** Reads source vector 16bit operand. */
virtual ConstVecLane16
- readVec16BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec16BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -257,8 +254,7 @@

/** Reads source vector 32bit operand. */
virtual ConstVecLane32
- readVec32BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec32BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -267,8 +263,7 @@

/** Reads source vector 64bit operand. */
virtual ConstVecLane64
- readVec64BitLaneOperand(const StaticInst *si, int idx) const
- override
+ readVec64BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -310,13 +305,15 @@
}
/** @} */

- VecElem readVecElemOperand(const StaticInst *si, int idx) const
override
+ VecElem
+ readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
return thread->readVecElem(reg);
}

- CCReg readCCRegOperand(const StaticInst *si, int idx) override
+ CCReg
+ readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isCCReg());
@@ -324,28 +321,31 @@
}

template<typename T>
- void setScalarResult(T&& t)
+ void
+setScalarResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::Scalar));
+ InstResult::ResultType::Scalar));
}

template<typename T>
- void setVecResult(T&& t)
+ void
+ setVecResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecReg));
+ InstResult::ResultType::VecReg));
}

template<typename T>
- void setVecElemResult(T&& t)
+ void
+ setVecElemResult(T&& t)
{
result.push(InstResult(std::forward<T>(t),
- InstResult::ResultType::VecElem));
+ InstResult::ResultType::VecElem));
}

- void setIntRegOperand(const StaticInst *si, int idx,
- IntReg val) override
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
@@ -353,8 +353,8 @@
setScalarResult(val);
}

- void setFloatRegOperand(const StaticInst *si, int idx,
- FloatReg val) override
+ void
+ setFloatRegOperand(const StaticInst *si, int idx, FloatRegVal val)
override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
@@ -362,8 +362,8 @@
setScalarResult(val);
}

- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) override
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
@@ -371,7 +371,8 @@
setScalarResult(val);
}

- void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ void
+ setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
@@ -379,8 +380,9 @@
setScalarResult((uint64_t)val);
}

- void setVecRegOperand(const StaticInst *si, int idx,
- const VecRegContainer& val) override
+ void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -388,8 +390,9 @@
setVecResult(val);
}

- void setVecElemOperand(const StaticInst *si, int idx,
- const VecElem val) override
+ void
+ setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
@@ -398,13 +401,15 @@
}

bool readPredicate() override { return thread->readPredicate(); }
- void setPredicate(bool val) override
+ void
+ setPredicate(bool val) override
{
thread->setPredicate(val);
}

TheISA::PCState pcState() const override { return thread->pcState(); }
- void pcState(const TheISA::PCState &val) override
+ void
+ pcState(const TheISA::PCState &val) override
{
DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
val, thread->pcState());
@@ -415,39 +420,47 @@
MicroPC microPC() { return thread->microPC(); }
//////////////////////////////////////////

- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal
+ readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}

- MiscReg readMiscReg(int misc_reg) override
+ RegVal
+ readMiscReg(int misc_reg) override
{
return thread->readMiscReg(misc_reg);
}

- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void
+ setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
- DPRINTF(Checker, "Setting misc reg %d with no effect to check
later\n", misc_reg);
+ DPRINTF(Checker, "Setting misc reg %d with no effect to check
later\n",
+ misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscRegNoEffect(misc_reg, val);
}

- void setMiscReg(int misc_reg, const MiscReg &val) override
+ void
+ setMiscReg(int misc_reg, const RegVal &val) override
{
- DPRINTF(Checker, "Setting misc reg %d with effect to check
later\n", misc_reg);
+ DPRINTF(Checker, "Setting misc reg %d with effect to check
later\n",
+ misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}

- MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
return thread->readMiscReg(reg.index());
}

- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val) override
+ void
+ setMiscRegOperand(const StaticInst *si, int idx,
+ const RegVal &val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -455,14 +468,15 @@
}

#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
override
+ RegVal
+ readRegOtherThread(const RegId &misc_reg, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
return 0;
}

- void setRegOtherThread(const RegId& misc_reg, MiscReg val,
- ThreadID tid) override
+ void
+ setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
override
{
panic("MIPS MT not defined for CheckerCPU.\n");
}
@@ -470,33 +484,36 @@

/////////////////////////////////////////

- void recordPCChange(const TheISA::PCState &val)
+ void
+ recordPCChange(const TheISA::PCState &val)
{
changedPC = true;
newPCState = val;
}

- void demapPage(Addr vaddr, uint64_t asn) override
+ void
+ demapPage(Addr vaddr, uint64_t asn) override
{
this->itb->demapPage(vaddr, asn);
this->dtb->demapPage(vaddr, asn);
}

// monitor/mwait funtions
- void armMonitor(Addr address) override
- { BaseCPU::armMonitor(0, address); }
+ void armMonitor(Addr address) override { BaseCPU::armMonitor(0,
address); }
bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
void mwaitAtomic(ThreadContext *tc) override
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
AddressMonitor *getAddrMonitor() override
{ return BaseCPU::getCpuAddrMonitor(0); }

- void demapInstPage(Addr vaddr, uint64_t asn)
+ void
+ demapInstPage(Addr vaddr, uint64_t asn)
{
this->itb->demapPage(vaddr, asn);
}

- void demapDataPage(Addr vaddr, uint64_t asn)
+ void
+ demapDataPage(Addr vaddr, uint64_t asn)
{
this->dtb->demapPage(vaddr, asn);
}
@@ -506,12 +523,12 @@
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res) override;

- unsigned int readStCondFailures() const override {
+ unsigned int
+ readStCondFailures() const override {
return thread->readStCondFailures();
}

- void setStCondFailures(unsigned int sc_failures) override
- {}
+ void setStCondFailures(unsigned int sc_failures) override {}
/////////////////////////////////////////////////////

Fault hwrei() override { return thread->hwrei(); }
@@ -522,7 +539,8 @@
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum, Fault *fault) override { }

- void handleError()
+ void
+ handleError()
{
if (exitOnError)
dumpAndExit();
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 975bd9f..90e6526 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -206,14 +206,19 @@
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
- { return actualTC->readIntReg(reg_idx); }
+ RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx);
}

- FloatReg readFloatReg(int reg_idx)
- { return actualTC->readFloatReg(reg_idx); }
+ FloatRegVal
+ readFloatReg(int reg_idx)
+ {
+ return actualTC->readFloatReg(reg_idx);
+ }

- FloatRegBits readFloatRegBits(int reg_idx)
- { return actualTC->readFloatRegBits(reg_idx); }
+ RegVal
+ readFloatRegBits(int reg_idx)
+ {
+ return actualTC->readFloatRegBits(reg_idx);
+ }

const VecRegContainer& readVecReg(const RegId& reg) const
{ return actualTC->readVecReg(reg); }
@@ -267,37 +272,43 @@
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }

- void setIntReg(int reg_idx, uint64_t val)
+ void
+ setIntReg(int reg_idx, RegVal val)
{
actualTC->setIntReg(reg_idx, val);
checkerTC->setIntReg(reg_idx, val);
}

- void setFloatReg(int reg_idx, FloatReg val)
+ void
+ setFloatReg(int reg_idx, FloatRegVal val)
{
actualTC->setFloatReg(reg_idx, val);
checkerTC->setFloatReg(reg_idx, val);
}

- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void
+ setFloatRegBits(int reg_idx, RegVal val)
{
actualTC->setFloatRegBits(reg_idx, val);
checkerTC->setFloatRegBits(reg_idx, val);
}

- void setVecReg(const RegId& reg, const VecRegContainer& val)
+ void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
{
actualTC->setVecReg(reg, val);
checkerTC->setVecReg(reg, val);
}

- void setVecElem(const RegId& reg, const VecElem& val)
+ void
+ setVecElem(const RegId& reg, const VecElem& val)
{
actualTC->setVecElem(reg, val);
checkerTC->setVecElem(reg, val);
}

- void setCCReg(int reg_idx, CCReg val)
+ void
+ setCCReg(int reg_idx, CCReg val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
@@ -308,7 +319,8 @@
{ return actualTC->pcState(); }

/** Sets this thread's PC state. */
- void pcState(const TheISA::PCState &val)
+ void
+ pcState(const TheISA::PCState &val)
{
DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
val, checkerTC->pcState());
@@ -317,13 +329,15 @@
return actualTC->pcState(val);
}

- void setNPC(Addr val)
+ void
+ setNPC(Addr val)
{
checkerTC->setNPC(val);
actualTC->setNPC(val);
}

- void pcStateNoRecord(const TheISA::PCState &val)
+ void
+ pcStateNoRecord(const TheISA::PCState &val)
{
return actualTC->pcState(val);
}
@@ -340,13 +354,14 @@
MicroPC microPC()
{ return actualTC->microPC(); }

- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }

- MiscReg readMiscReg(int misc_reg)
+ RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }

- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void
+ setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both
Checker"
" and O3..\n", misc_reg);
@@ -354,7 +369,8 @@
actualTC->setMiscRegNoEffect(misc_reg, val);
}

- void setMiscReg(int misc_reg, const MiscReg &val)
+ void
+ setMiscReg(int misc_reg, const RegVal &val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);
@@ -362,46 +378,68 @@
actualTC->setMiscReg(misc_reg, val);
}

- RegId flattenRegId(const RegId& regId) const {
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
return actualTC->flattenRegId(regId);
}

unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }

- void setStCondFailures(unsigned sc_failures)
+ void
+ setStCondFailures(unsigned sc_failures)
{
actualTC->setStCondFailures(sc_failures);
}

Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }

- uint64_t readIntRegFlat(int idx)
- { return actualTC->readIntRegFlat(idx); }
+ RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx);
}

- void setIntRegFlat(int idx, uint64_t val)
- { actualTC->setIntRegFlat(idx, val); }
+ void
+ setIntRegFlat(int idx, RegVal val)
+ {
+ actualTC->setIntRegFlat(idx, val);
+ }

- FloatReg readFloatRegFlat(int idx)
- { return actualTC->readFloatRegFlat(idx); }
+ FloatRegVal
+ readFloatRegFlat(int idx)
+ {
+ return actualTC->readFloatRegFlat(idx);
+ }

- void setFloatRegFlat(int idx, FloatReg val)
- { actualTC->setFloatRegFlat(idx, val); }
+ void
+ setFloatRegFlat(int idx, FloatRegVal val)
+ {
+ actualTC->setFloatRegFlat(idx, val);
+ }

- FloatRegBits readFloatRegBitsFlat(int idx)
- { return actualTC->readFloatRegBitsFlat(idx); }
+ RegVal readFloatRegBitsFlat(int idx)
+ {
+ return actualTC->readFloatRegBitsFlat(idx);
+ }

- void setFloatRegBitsFlat(int idx, FloatRegBits val)
- { actualTC->setFloatRegBitsFlat(idx, val); }
+ void
+ setFloatRegBitsFlat(int idx, RegVal val)
+ {
+ actualTC->setFloatRegBitsFlat(idx, val);
+ }

- const VecRegContainer& readVecRegFlat(int idx) const
- { return actualTC->readVecRegFlat(idx); }
+ const VecRegContainer &
+ readVecRegFlat(int idx) const
+ {
+ return actualTC->readVecRegFlat(idx);
+ }

/**
* Read vector register for modification, flat indexing.
*/
- VecRegContainer& getWritableVecRegFlat(int idx)
- { return actualTC->getWritableVecRegFlat(idx); }
+ VecRegContainer &
+ getWritableVecRegFlat(int idx)
+ {
+ return actualTC->getWritableVecRegFlat(idx);
+ }

void setVecRegFlat(int idx, const VecRegContainer& val)
{ actualTC->setVecRegFlat(idx, val); }
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 59d7414..df1c020 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -72,11 +72,7 @@
*/
class ExecContext {
public:
- typedef TheISA::IntReg IntReg;
typedef TheISA::PCState PCState;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;

typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
@@ -90,11 +86,11 @@
*/

/** Reads an integer register. */
- virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
+ virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;

/** Sets an integer register to a value. */
virtual void setIntRegOperand(const StaticInst *si,
- int idx, IntReg val) = 0;
+ int idx, RegVal val) = 0;

/** @} */

@@ -105,21 +101,20 @@
*/

/** Reads a floating point register of single register width. */
- virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) =
0;
+ virtual FloatRegVal readFloatRegOperand(const StaticInst *si, int idx)
= 0;

/** Reads a floating point register in its binary format, instead
* of by value. */
- virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
- int idx) = 0;
+ virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx)
= 0;

/** Sets a floating point register of single width to a value. */
virtual void setFloatRegOperand(const StaticInst *si,
- int idx, FloatReg val) = 0;
+ int idx, FloatRegVal val) = 0;

/** Sets the bits of a floating point register of single width
* to a binary value. */
virtual void setFloatRegOperandBits(const StaticInst *si,
- int idx, FloatRegBits val) = 0;
+ int idx, RegVal val) = 0;

/** @} */

@@ -192,21 +187,21 @@
* @{
* @name Misc Register Interfaces
*/
- virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
+ virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
virtual void setMiscRegOperand(const StaticInst *si,
- int idx, const MiscReg &val) = 0;
+ int idx, const RegVal &val) = 0;

/**
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ virtual RegVal readMiscReg(int misc_reg) = 0;

/**
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;

/** @} */

@@ -333,10 +328,10 @@
*/

#if THE_ISA == MIPS_ISA
- virtual MiscReg readRegOtherThread(const RegId& reg,
- ThreadID tid = InvalidThreadID) = 0;
- virtual void setRegOtherThread(const RegId& reg, MiscReg val,
- ThreadID tid = InvalidThreadID) = 0;
+ virtual RegVal readRegOtherThread(const RegId &reg,
+ ThreadID tid=InvalidThreadID) = 0;
+ virtual void setRegOtherThread(const RegId& reg, RegVal val,
+ ThreadID tid=InvalidThreadID) = 0;
#endif

/** @} */
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 012cccd..cfb0d5e 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -823,9 +823,6 @@
static void
updateKvmStateFPUCommon(ThreadContext *tc, T &fpu)
{
- static_assert(sizeof(X86ISA::FloatRegBits) == 8,
- "Unexpected size of X86ISA::FloatRegBits");
-
fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR);
fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW);
// No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read
@@ -849,9 +846,9 @@
// TODO: We should update the MMX state

for (int i = 0; i < 16; ++i) {
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][0] =
+ *(uint64_t *)&fpu.xmm[i][0] =
tc->readFloatRegBits(FLOATREG_XMM_LOW(i));
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][8] =
+ *(uint64_t *)&fpu.xmm[i][8] =
tc->readFloatRegBits(FLOATREG_XMM_HIGH(i));
}
}
@@ -1047,9 +1044,6 @@
{
const unsigned top((fpu.fsw >> 11) & 0x7);

- static_assert(sizeof(X86ISA::FloatRegBits) == 8,
- "Unexpected size of X86ISA::FloatRegBits");
-
for (int i = 0; i < 8; ++i) {
const unsigned reg_idx((i + top) & 0x7);
const double value(X86ISA::loadFloat80(fpu.fpr[i]));
@@ -1074,9 +1068,9 @@

for (int i = 0; i < 16; ++i) {
tc->setFloatRegBits(FLOATREG_XMM_LOW(i),
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][0]);
+ *(uint64_t *)&fpu.xmm[i][0]);
tc->setFloatRegBits(FLOATREG_XMM_HIGH(i),
- *(X86ISA::FloatRegBits *)&fpu.xmm[i][8]);
+ *(uint64_t *)&fpu.xmm[i][8]);
}
}

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 6ac0df5..44b0bd7 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -121,7 +121,7 @@
return NoFault;
}

- IntReg
+ RegVal
readIntRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -129,7 +129,7 @@
return thread.readIntReg(reg.index());
}

- TheISA::FloatReg
+ FloatRegVal
readFloatRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -137,7 +137,7 @@
return thread.readFloatReg(reg.index());
}

- TheISA::FloatRegBits
+ RegVal
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -145,7 +145,7 @@
return thread.readFloatRegBits(reg.index());
}

- const TheISA::VecRegContainer&
+ const TheISA::VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -153,7 +153,7 @@
return thread.readVecReg(reg);
}

- TheISA::VecRegContainer&
+ TheISA::VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
@@ -170,7 +170,7 @@
}

void
- setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isIntReg());
@@ -178,8 +178,7 @@
}

void
- setFloatRegOperand(const StaticInst *si, int idx,
- TheISA::FloatReg val) override
+ setFloatRegOperand(const StaticInst *si, int idx, FloatRegVal val)
override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
@@ -187,8 +186,7 @@
}

void
- setFloatRegOperandBits(const StaticInst *si, int idx,
- TheISA::FloatRegBits val) override
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
@@ -249,8 +247,7 @@
/** Write a lane of the destination vector operand. */
template <typename LD>
void
- setVecLaneOperandT(const StaticInst *si, int idx,
- const LD& val)
+ setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -315,25 +312,25 @@
thread.pcState(val);
}

- TheISA::MiscReg
+ RegVal
readMiscRegNoEffect(int misc_reg) const
{
return thread.readMiscRegNoEffect(misc_reg);
}

- TheISA::MiscReg
+ RegVal
readMiscReg(int misc_reg) override
{
return thread.readMiscReg(misc_reg);
}

void
- setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
+ setMiscReg(int misc_reg, const RegVal &val) override
{
thread.setMiscReg(misc_reg, val);
}

- TheISA::MiscReg
+ RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -343,7 +340,7 @@

void
setMiscRegOperand(const StaticInst *si, int idx,
- const TheISA::MiscReg &val) override
+ const RegVal &val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -372,7 +369,7 @@

void
syscall(int64_t callnum, Fault *fault) override
- {
+ {
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.\n");

@@ -427,8 +424,8 @@
BaseCPU *getCpuPtr() { return &cpu; }

/* MIPS: other thread register reading/writing */
- uint64_t
- readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
+ RegVal
+ readRegOtherThread(const RegId &reg, ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
@@ -450,8 +447,8 @@
}

void
- setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
- ThreadID tid = InvalidThreadID)
+ setRegOtherThread(const RegId &reg, const RegVal &val,
+ ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c4bc13f..1668b3a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1244,14 +1244,14 @@
}

template <class Impl>
-TheISA::MiscReg
+RegVal
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}

template <class Impl>
-TheISA::MiscReg
+RegVal
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
miscRegfileReads++;
@@ -1261,7 +1261,7 @@
template <class Impl>
void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
- const TheISA::MiscReg &val, ThreadID tid)
+ const RegVal &val, ThreadID tid)
{
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
@@ -1269,14 +1269,14 @@
template <class Impl>
void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
- const TheISA::MiscReg &val, ThreadID tid)
+ const RegVal &val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
}

template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
{
intRegfileReads++;
@@ -1284,7 +1284,7 @@
}

template <class Impl>
-FloatReg
+FloatRegVal
FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
{
fpRegfileReads++;
@@ -1292,7 +1292,7 @@
}

template <class Impl>
-FloatRegBits
+RegVal
FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
{
fpRegfileReads++;
@@ -1335,7 +1335,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
intRegfileWrites++;
regFile.setIntReg(phys_reg, val);
@@ -1343,7 +1343,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
+FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatRegVal val)
{
fpRegfileWrites++;
regFile.setFloatReg(phys_reg, val);
@@ -1351,7 +1351,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
{
fpRegfileWrites++;
regFile.setFloatRegBits(phys_reg, val);
@@ -1382,7 +1382,7 @@
}

template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
intRegfileReads++;
@@ -1393,7 +1393,7 @@
}

template <class Impl>
-float
+FloatRegVal
FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
@@ -1404,7 +1404,7 @@
}

template <class Impl>
-uint64_t
+RegVal
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
@@ -1457,7 +1457,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
{
intRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1468,7 +1468,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatReg(int reg_idx, FloatRegVal val, ThreadID
tid)
{
fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1479,7 +1479,7 @@

template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID
tid)
+FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, RegVal val, ThreadID tid)
{
fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1589220..a52e5ed 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -382,28 +382,26 @@
/** Register accessors. Index refers to the physical register index.
*/

/** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
+ RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;

/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
+ RegVal readMiscReg(int misc_reg, ThreadID tid);

/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);

/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
- ThreadID tid);
+ void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);

- uint64_t readIntReg(PhysRegIdPtr phys_reg);
+ RegVal readIntReg(PhysRegIdPtr phys_reg);

- TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
+ FloatRegVal readFloatReg(PhysRegIdPtr phys_reg);

- TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
+ RegVal readFloatRegBits(PhysRegIdPtr phys_reg);

const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;

@@ -447,11 +445,11 @@

TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);

- void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
+ void setIntReg(PhysRegIdPtr phys_reg, RegVal val);

- void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
+ void setFloatReg(PhysRegIdPtr phys_reg, FloatRegVal val);

- void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
+ void setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val);

void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);

@@ -459,11 +457,11 @@

void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);

- uint64_t readArchIntReg(int reg_idx, ThreadID tid);
+ RegVal readArchIntReg(int reg_idx, ThreadID tid);

- float readArchFloatReg(int reg_idx, ThreadID tid);
+ FloatRegVal readArchFloatReg(int reg_idx, ThreadID tid);

- uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
+ RegVal readArchFloatRegInt(int reg_idx, ThreadID tid);

const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
/** Read architectural vector register for modification. */
@@ -500,11 +498,11 @@
* architected register first, then accesses that physical
* register.
*/
- void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);

- void setArchFloatReg(int reg_idx, float val, ThreadID tid);
+ void setArchFloatReg(int reg_idx, FloatRegVal val, ThreadID tid);

- void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchFloatRegInt(int reg_idx, RegVal val, ThreadID tid);

void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID
tid);

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 47dc830..6e95d2f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,17 +66,11 @@
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;

- /** Misc register type. */
- typedef TheISA::MiscReg MiscReg;
-
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
@@ -114,7 +108,7 @@
using BaseDynInst<Impl>::_destRegIdx;

/** Values to be written to the destination misc. registers. */
- std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+ std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;

/** Indexes of the destination misc. registers. They are needed to
defer
* the write accesses to the misc. registers until the commit stage,
when
@@ -142,7 +136,8 @@
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscReg(int misc_reg)
+ RegVal
+ readMiscReg(int misc_reg)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
@@ -150,7 +145,8 @@
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void
+ setMiscReg(int misc_reg, const RegVal &val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
@@ -174,7 +170,8 @@
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx)
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isMiscReg());
@@ -184,8 +181,8 @@
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val)
+ void
+ setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -193,7 +190,8 @@
}

/** Called at the commit stage to update the misc. registers. */
- void updateMiscRegs()
+ void
+ updateMiscRegs()
{
// @todo: Pretty convoluted way to avoid squashing from happening
when
// using the TC during an instruction's execution (specifically for
@@ -268,17 +266,20 @@
// storage (which is pretty hard to imagine they would have reason
// to do).

- IntReg readIntRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}

- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
+ FloatRegVal
+ readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}

- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
@@ -374,20 +375,22 @@
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}

- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+ void
+ setFloatRegOperand(const StaticInst *si, int idx, FloatRegVal val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}

- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val)
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
@@ -416,13 +419,15 @@
}

#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid)
+ RegVal
+ readRegOtherThread(const RegId& misc_reg, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
return 0;
}

- void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID
tid)
+ void
+ setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
panic("MIPS MT not defined for O3 CPU.\n");
}
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 7feec93..f9d8b59 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,9 +65,6 @@
{
private:

- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
@@ -80,12 +77,12 @@
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;

typedef union {
- FloatReg d;
- FloatRegBits q;
+ FloatRegVal d;
+ RegVal q;
} PhysFloatReg;

/** Integer register file. */
- std::vector<IntReg> intRegFile;
+ std::vector<RegVal> intRegFile;
std::vector<PhysRegId> intRegIds;

/** Floating point register file. */
@@ -178,7 +175,8 @@
}

/** Reads an integer register. */
- uint64_t readIntReg(PhysRegIdPtr phys_reg) const
+ RegVal
+ readIntReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isIntPhysReg());

@@ -188,7 +186,8 @@
}

/** Reads a floating point register (double precision). */
- FloatReg readFloatReg(PhysRegIdPtr phys_reg) const
+ FloatRegVal
+ readFloatReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isFloatPhysReg());

@@ -199,21 +198,22 @@
return floatRegFile[phys_reg->index()].d;
}

- FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
+ RegVal
+ readFloatRegBits(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isFloatPhysReg());

- FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q;
+ RegVal floatRegBits = floatRegFile[phys_reg->index()].q;

DPRINTF(IEW, "RegFile: Access to float register %i as int, "
- "has data %#x\n", phys_reg->index(),
- (uint64_t)floatRegBits);
+ "has data %#x\n", phys_reg->index(), floatRegBits);

return floatRegBits;
}

/** Reads a vector register. */
- const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
+ const VecRegContainer &
+ readVecReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysReg());

@@ -225,7 +225,8 @@
}

/** Reads a vector register for modification. */
- VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
+ VecRegContainer &
+ getWritableVecReg(PhysRegIdPtr phys_reg)
{
/* const_cast for not duplicating code above. */
return const_cast<VecRegContainer&>(readVecReg(phys_reg));
@@ -262,7 +263,8 @@
}

/** Reads a vector element. */
- const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
+ const VecElem &
+ readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysElem());
auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
@@ -275,7 +277,8 @@
}

/** Reads a condition-code register. */
- CCReg readCCReg(PhysRegIdPtr phys_reg)
+ CCReg
+ readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());

@@ -287,7 +290,8 @@
}

/** Sets an integer register to the given value. */
- void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
+ void
+ setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isIntPhysReg());

@@ -299,7 +303,8 @@
}

/** Sets a double precision floating point register to the given
value. */
- void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
+ void
+ setFloatReg(PhysRegIdPtr phys_reg, FloatRegVal val)
{
assert(phys_reg->isFloatPhysReg());

@@ -310,7 +315,8 @@
floatRegFile[phys_reg->index()].d = val;
}

- void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
+ void
+ setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isFloatPhysReg());

@@ -322,7 +328,8 @@
}

/** Sets a vector register to the given value. */
- void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
+ void
+ setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
{
assert(phys_reg->isVectorPhysReg());

@@ -333,7 +340,8 @@
}

/** Sets a vector register to the given value. */
- void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
+ void
+ setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
{
assert(phys_reg->isVectorPhysElem());

@@ -345,7 +353,8 @@
}

/** Sets a condition-code register to the given value. */
- void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+ void
+ setCCReg(PhysRegIdPtr phys_reg, CCReg val)
{
assert(phys_reg->isCCPhysReg());

@@ -367,12 +376,12 @@
*/
IdRange getRegIds(RegClass cls);

- /**
- * Get the true physical register id.
- * As many parts work with PhysRegIdPtr, we need to be able to produce
- * the pointer out of just class and register idx.
- */
- PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
+ /**
+ * Get the true physical register id.
+ * As many parts work with PhysRegIdPtr, we need to be able to produce
+ * the pointer out of just class and register idx.
+ */
+ PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
};


diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 2256a8a..c55ea5d 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -175,33 +175,44 @@
virtual void clearArchRegs();

/** Reads an integer register. */
- virtual uint64_t readReg(int reg_idx) {
+ virtual RegVal
+ readReg(int reg_idx)
+ {
return readIntRegFlat(flattenRegId(RegId(IntRegClass,
reg_idx)).index());
}
- virtual uint64_t readIntReg(int reg_idx) {
+ virtual RegVal
+ readIntReg(int reg_idx)
+ {
return readIntRegFlat(flattenRegId(RegId(IntRegClass,
reg_idx)).index());
}

- virtual FloatReg readFloatReg(int reg_idx) {
+ virtual FloatRegVal
+ readFloatReg(int reg_idx)
+ {
return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index());
}

- virtual FloatRegBits readFloatRegBits(int reg_idx) {
+ virtual RegVal readFloatRegBits(int reg_idx)
+ {
return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index());
}

- virtual const VecRegContainer& readVecReg(const RegId& id) const {
+ virtual const VecRegContainer &
+ readVecReg(const RegId& id) const
+ {
return readVecRegFlat(flattenRegId(id).index());
}

/**
* Read vector register operand for modification, hierarchical
indexing.
*/
- virtual VecRegContainer& getWritableVecReg(const RegId& id) {
+ virtual VecRegContainer &
+ getWritableVecReg(const RegId& id)
+ {
return getWritableVecRegFlat(flattenRegId(id).index());
}

@@ -264,29 +275,41 @@
}

/** Sets an integer register to a value. */
- virtual void setIntReg(int reg_idx, uint64_t val) {
+ virtual void
+ setIntReg(int reg_idx, RegVal val)
+ {
setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(),
val);
}

- virtual void setFloatReg(int reg_idx, FloatReg val) {
+ virtual void
+ setFloatReg(int reg_idx, FloatRegVal val)
+ {
setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index(), val);
}

- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
+ virtual void
+ setFloatRegBits(int reg_idx, RegVal val)
+ {
setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index(), val);
}

- virtual void setVecReg(const RegId& reg, const VecRegContainer& val) {
+ virtual void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
+ {
setVecRegFlat(flattenRegId(reg).index(), val);
}

- virtual void setVecElem(const RegId& reg, const VecElem& val) {
+ virtual void
+ setVecElem(const RegId& reg, const VecElem& val)
+ {
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}

- virtual void setCCReg(int reg_idx, CCReg val) {
+ virtual void
+ setCCReg(int reg_idx, CCReg val)
+ {
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(),
val);
}

@@ -312,20 +335,20 @@
{ return cpu->microPC(thread->threadId()); }

/** Reads a miscellaneous register. */
- virtual MiscReg readMiscRegNoEffect(int misc_reg) const
+ virtual RegVal readMiscRegNoEffect(int misc_reg) const
{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }

/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
- virtual MiscReg readMiscReg(int misc_reg)
+ virtual RegVal readMiscReg(int misc_reg)
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }

/** Sets a misc. register. */
- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+ virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);

/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
- virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual void setMiscReg(int misc_reg, const RegVal &val);

virtual RegId flattenRegId(const RegId& regId) const;

@@ -346,7 +369,8 @@
virtual Counter readFuncExeInst() { return thread->funcExeInst; }

/** Returns pointer to the quiesce event. */
- virtual EndQuiesceEvent *getQuiesceEvent()
+ virtual EndQuiesceEvent *
+ getQuiesceEvent()
{
return this->thread->quiesceEvent;
}
@@ -355,20 +379,21 @@
* similar is currently writing to the thread context and doesn't want
* reset all the state (see noSquashFromTC).
*/
- inline void conditionalSquash()
+ inline void
+ conditionalSquash()
{
if (!thread->trapPending && !thread->noSquashFromTC)
cpu->squashFromTC(thread->threadId());
}

- virtual uint64_t readIntRegFlat(int idx);
- virtual void setIntRegFlat(int idx, uint64_t val);
+ virtual RegVal readIntRegFlat(int idx);
+ virtual void setIntRegFlat(int idx, RegVal val);

- virtual FloatReg readFloatRegFlat(int idx);
- virtual void setFloatRegFlat(int idx, FloatReg val);
+ virtual FloatRegVal readFloatRegFlat(int idx);
+ virtual void setFloatRegFlat(int idx, FloatRegVal val);

- virtual FloatRegBits readFloatRegBitsFlat(int idx);
- virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
+ virtual RegVal readFloatRegBitsFlat(int idx);
+ virtual void setFloatRegBitsFlat(int idx, RegVal val);

virtual const VecRegContainer& readVecRegFlat(int idx) const;
/** Read vector register operand for modification, flat indexing. */
@@ -376,7 +401,8 @@
virtual void setVecRegFlat(int idx, const VecRegContainer& val);

template <typename VecElem>
- VecLaneT<VecElem, true> readVecLaneFlat(int idx, int lId) const
+ VecLaneT<VecElem, true>
+ readVecLaneFlat(int idx, int lId) const
{
return cpu->template readArchVecLane<VecElem>(idx, lId,
thread->threadId());
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index d9f84fb..9852cb0 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -193,21 +193,21 @@
}

template <class Impl>
-uint64_t
+RegVal
O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
{
return cpu->readArchIntReg(reg_idx, thread->threadId());
}

template <class Impl>
-TheISA::FloatReg
+FloatRegVal
O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
{
return cpu->readArchFloatReg(reg_idx, thread->threadId());
}

template <class Impl>
-TheISA::FloatRegBits
+RegVal
O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
{
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
@@ -244,7 +244,7 @@

template <class Impl>
void
-O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
+O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
{
cpu->setArchIntReg(reg_idx, val, thread->threadId());

@@ -253,7 +253,7 @@

template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
+O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatRegVal val)
{
cpu->setArchFloatReg(reg_idx, val, thread->threadId());

@@ -262,7 +262,7 @@

template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
+O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
{
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());

@@ -323,7 +323,7 @@

template <class Impl>
void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());

@@ -333,7 +333,7 @@
#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 13c44ac..af6485f 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -60,9 +60,6 @@

class SimpleExecContext : public ExecContext {
protected:
- typedef TheISA::MiscReg MiscReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -174,7 +171,8 @@
{ }

/** Reads an integer register. */
- IntReg readIntRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readIntRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
@@ -183,7 +181,8 @@
}

/** Sets an integer register to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
override
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -192,7 +191,8 @@
}

/** Reads a floating point register of single register width. */
- FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
+ FloatRegVal
+ readFloatRegOperand(const StaticInst *si, int idx) override
{
numFpRegReads++;
const RegId& reg = si->srcRegIdx(idx);
@@ -202,7 +202,8 @@

/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
override
+ RegVal
+ readFloatRegOperandBits(const StaticInst *si, int idx) override
{
numFpRegReads++;
const RegId& reg = si->srcRegIdx(idx);
@@ -211,8 +212,8 @@
}

/** Sets a floating point register of single width to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx,
- FloatReg val) override
+ void
+ setFloatRegOperand(const StaticInst *si, int idx, FloatRegVal val)
override
{
numFpRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -222,8 +223,8 @@

/** Sets the bits of a floating point register of single width
* to a binary value. */
- void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) override
+ void
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
override
{
numFpRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -232,7 +233,7 @@
}

/** Reads a vector register. */
- const VecRegContainer&
+ const VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
numVecRegReads++;
@@ -242,7 +243,7 @@
}

/** Reads a vector register for modification. */
- VecRegContainer&
+ VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
numVecRegWrites++;
@@ -252,8 +253,9 @@
}

/** Sets a vector register to a value. */
- void setVecRegOperand(const StaticInst *si, int idx,
- const VecRegContainer& val) override
+ void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer& val) override
{
numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -331,7 +333,8 @@
/** @} */

/** Reads an element of a vector register. */
- VecElem readVecElemOperand(const StaticInst *si, int idx) const
override
+ VecElem
+ readVecElemOperand(const StaticInst *si, int idx) const override
{
numVecRegReads++;
const RegId& reg = si->destRegIdx(idx);
@@ -340,8 +343,9 @@
}

/** Sets an element of a vector register to a value. */
- void setVecElemOperand(const StaticInst *si, int idx,
- const VecElem val) override
+ void
+ setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) override
{
numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -349,7 +353,8 @@
thread->setVecElem(reg, val);
}

- CCReg readCCRegOperand(const StaticInst *si, int idx) override
+ CCReg
+ readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
const RegId& reg = si->srcRegIdx(idx);
@@ -357,7 +362,8 @@
return thread->readCCReg(reg.index());
}

- void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ void
+ setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -365,7 +371,8 @@
thread->setCCReg(reg.index(), val);
}

- MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
+ RegVal
+ readMiscRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
const RegId& reg = si->srcRegIdx(idx);
@@ -373,8 +380,9 @@
return thread->readMiscReg(reg.index());
}

- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val) override
+ void
+ setMiscRegOperand(const StaticInst *si, int idx,
+ const RegVal &val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -386,7 +394,8 @@
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- MiscReg readMiscReg(int misc_reg) override
+ RegVal
+ readMiscReg(int misc_reg) override
{
numIntRegReads++;
return thread->readMiscReg(misc_reg);
@@ -396,37 +405,43 @@
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- void setMiscReg(int misc_reg, const MiscReg &val) override
+ void
+ setMiscReg(int misc_reg, const RegVal &val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
}

- PCState pcState() const override
+ PCState
+ pcState() const override
{
return thread->pcState();
}

- void pcState(const PCState &val) override
+ void
+ pcState(const PCState &val) override
{
thread->pcState(val);
}


- Fault readMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags) override
+ Fault
+ readMem(Addr addr, uint8_t *data, unsigned int size,
+ Request::Flags flags) override
{
return cpu->readMem(addr, data, size, flags);
}

- Fault initiateMemRead(Addr addr, unsigned int size,
- Request::Flags flags) override
+ Fault
+ initiateMemRead(Addr addr, unsigned int size,
+ Request::Flags flags) override
{
return cpu->initiateMemRead(addr, size, flags);
}

- Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
- Request::Flags flags, uint64_t *res) override
+ Fault
+ writeMem(uint8_t *data, unsigned int size, Addr addr,
+ Request::Flags flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}
@@ -434,7 +449,8 @@
/**
* Sets the number of consecutive store conditional failures.
*/
- void setStCondFailures(unsigned int sc_failures) override
+ void
+ setStCondFailures(unsigned int sc_failures) override
{
thread->setStCondFailures(sc_failures);
}
@@ -442,7 +458,8 @@
/**
* Returns the number of consecutive store conditional failures.
*/
- unsigned int readStCondFailures() const override
+ unsigned int
+ readStCondFailures() const override
{
return thread->readStCondFailures();
}
@@ -450,7 +467,8 @@
/**
* Executes a syscall specified by the callnum.
*/
- void syscall(int64_t callnum, Fault *fault) override
+ void
+ syscall(int64_t callnum, Fault *fault) override
{
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.");
@@ -459,35 +477,28 @@
}

/** Returns a pointer to the ThreadContext. */
- ThreadContext *tcBase() override
- {
- return thread->getTC();
- }
+ ThreadContext *tcBase() override { return thread->getTC(); }

/**
* Somewhat Alpha-specific function that handles returning from an
* error or interrupt.
*/
- Fault hwrei() override
- {
- return thread->hwrei();
- }
+ Fault hwrei() override { return thread->hwrei(); }

/**
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
*/
- bool simPalCheck(int palFunc) override
+ bool
+ simPalCheck(int palFunc) override
{
return thread->simPalCheck(palFunc);
}

- bool readPredicate() override
- {
- return thread->readPredicate();
- }
+ bool readPredicate() override { return thread->readPredicate(); }

- void setPredicate(bool val) override
+ void
+ setPredicate(bool val) override
{
thread->setPredicate(val);

@@ -499,47 +510,52 @@
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
- void demapPage(Addr vaddr, uint64_t asn) override
+ void
+ demapPage(Addr vaddr, uint64_t asn) override
{
thread->demapPage(vaddr, asn);
}

- void armMonitor(Addr address) override
+ void
+ armMonitor(Addr address) override
{
cpu->armMonitor(thread->threadId(), address);
}

- bool mwait(PacketPtr pkt) override
+ bool
+ mwait(PacketPtr pkt) override
{
return cpu->mwait(thread->threadId(), pkt);
}

- void mwaitAtomic(ThreadContext *tc) override
+ void
+ mwaitAtomic(ThreadContext *tc) override
{
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
}

- AddressMonitor *getAddrMonitor() override
+ AddressMonitor *
+ getAddrMonitor() override
{
return cpu->getCpuAddrMonitor(thread->threadId());
}

#if THE_ISA == MIPS_ISA
- MiscReg readRegOtherThread(const RegId& reg,
- ThreadID tid = InvalidThreadID)
+ RegVal
+ readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID)
override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}

- void setRegOtherThread(const RegId& reg, MiscReg val,
- ThreadID tid = InvalidThreadID) override
+ void
+ setRegOtherThread(const RegId& reg, RegVal val,
+ ThreadID tid=InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
-
#endif

};
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3c64082..41e6794 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -99,9 +99,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::MiscReg MiscReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -110,10 +107,10 @@

protected:
union {
- FloatReg f[TheISA::NumFloatRegs];
- FloatRegBits i[TheISA::NumFloatRegs];
+ FloatRegVal f[TheISA::NumFloatRegs];
+ RegVal i[TheISA::NumFloatRegs];
} floatRegs;
- TheISA::IntReg intRegs[TheISA::NumIntRegs];
+ RegVal intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
#ifdef ISA_HAS_CC_REGS
TheISA::CCReg ccRegs[TheISA::NumCCRegs];
@@ -243,7 +240,8 @@
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
+ RegVal
+ readIntReg(int reg_idx)
{
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
@@ -253,21 +251,23 @@
return regVal;
}

- FloatReg readFloatReg(int reg_idx)
+ FloatRegVal
+ readFloatReg(int reg_idx)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatReg regVal(readFloatRegFlat(flatIndex));
+ FloatRegVal regVal(readFloatRegFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
return regVal;
}

- FloatRegBits readFloatRegBits(int reg_idx)
+ RegVal
+ readFloatRegBits(int reg_idx)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
+ RegVal regVal(readFloatRegBitsFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
return regVal;
@@ -381,7 +381,8 @@
#endif
}

- void setIntReg(int reg_idx, uint64_t val)
+ void
+ setIntReg(int reg_idx, RegVal val)
{
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
@@ -390,7 +391,8 @@
setIntRegFlat(flatIndex, val);
}

- void setFloatReg(int reg_idx, FloatReg val)
+ void
+ setFloatReg(int reg_idx, FloatRegVal val)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
@@ -399,7 +401,8 @@
reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
}

- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void
+ setFloatRegBits(int reg_idx, RegVal val)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
@@ -411,7 +414,8 @@
reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
}

- void setVecReg(const RegId& reg, const VecRegContainer& val)
+ void
+ setVecReg(const RegId& reg, const VecRegContainer& val)
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
@@ -420,7 +424,8 @@
reg.index(), flatIndex, val.print());
}

- void setVecElem(const RegId& reg, const VecElem& val)
+ void
+ setVecElem(const RegId& reg, const VecElem& val)
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
@@ -429,7 +434,8 @@
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
}

- void setCCReg(int reg_idx, CCReg val)
+ void
+ setCCReg(int reg_idx, CCReg val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -494,26 +500,26 @@
predicate = val;
}

- MiscReg
- readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
+ RegVal
+ readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const
{
return isa->readMiscRegNoEffect(misc_reg);
}

- MiscReg
- readMiscReg(int misc_reg, ThreadID tid = 0)
+ RegVal
+ readMiscReg(int misc_reg, ThreadID tid=0)
{
return isa->readMiscReg(misc_reg, tc);
}

void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
+ setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
{
return isa->setMiscRegNoEffect(misc_reg, val);
}

void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
+ setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
{
return isa->setMiscReg(misc_reg, val, tc);
}
@@ -529,57 +535,62 @@
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }

- void syscall(int64_t callnum, Fault *fault)
+ void
+ syscall(int64_t callnum, Fault *fault)
{
process->syscall(callnum, tc, fault);
}

- uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
- void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
+ RegVal readIntRegFlat(int idx) { return intRegs[idx]; }
+ void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; }

- FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
- void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
+ FloatRegVal readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
+ void setFloatRegFlat(int idx, FloatRegVal val) { floatRegs.f[idx] =
val; }

- FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
- void setFloatRegBitsFlat(int idx, FloatRegBits val) {
- floatRegs.i[idx] = val;
- }
+ RegVal readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
+ void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs.i[idx] =
val; }

- const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
+ const VecRegContainer &
+ readVecRegFlat(const RegIndex& reg) const
{
return vecRegs[reg];
}

- VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
+ VecRegContainer &
+ getWritableVecRegFlat(const RegIndex& reg)
{
return vecRegs[reg];
}

- void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
+ void
+ setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
{
vecRegs[reg] = val;
}

template <typename T>
- VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
+ VecLaneT<T, true>
+ readVecLaneFlat(const RegIndex& reg, int lId) const
{
return vecRegs[reg].laneView<T>(lId);
}

template <typename LD>
- void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
+ void
+ setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
{
vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
}

- const VecElem& readVecElemFlat(const RegIndex& reg,
- const ElemIndex& elemIndex) const
+ const VecElem &
+ readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
}

- void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
- const VecElem val)
+ void
+ setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
+ const VecElem val)
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index bf25cd6..2d907a0 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -61,8 +61,8 @@

// First loop through the integer registers.
for (int i = 0; i < TheISA::NumIntRegs; ++i) {
- TheISA::IntReg t1 = one->readIntReg(i);
- TheISA::IntReg t2 = two->readIntReg(i);
+ RegVal t1 = one->readIntReg(i);
+ RegVal t2 = two->readIntReg(i);
if (t1 != t2)
panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -70,8 +70,8 @@

// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
- TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
- TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
+ RegVal t1 = one->readFloatRegBits(i);
+ RegVal t2 = two->readFloatRegBits(i);
if (t1 != t2)
panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -87,8 +87,8 @@
i, t1, t2);
}
for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
- TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
- TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
+ RegVal t1 = one->readMiscRegNoEffect(i);
+ RegVal t2 = two->readMiscRegNoEffect(i);
if (t1 != t2)
panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -155,7 +155,7 @@
{
using namespace TheISA;

- FloatRegBits floatRegs[NumFloatRegs];
+ RegVal floatRegs[NumFloatRegs];
for (int i = 0; i < NumFloatRegs; ++i)
floatRegs[i] = tc.readFloatRegBitsFlat(i);
// This is a bit ugly, but needed to maintain backwards
@@ -168,7 +168,7 @@
}
SERIALIZE_CONTAINER(vecRegs);

- IntReg intRegs[NumIntRegs];
+ RegVal intRegs[NumIntRegs];
for (int i = 0; i < NumIntRegs; ++i)
intRegs[i] = tc.readIntRegFlat(i);
SERIALIZE_ARRAY(intRegs, NumIntRegs);
@@ -190,7 +190,7 @@
{
using namespace TheISA;

- FloatRegBits floatRegs[NumFloatRegs];
+ RegVal floatRegs[NumFloatRegs];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
@@ -203,7 +203,7 @@
tc.setVecRegFlat(i, vecRegs[i]);
}

- IntReg intRegs[NumIntRegs];
+ RegVal intRegs[NumIntRegs];
UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
for (int i = 0; i < NumIntRegs; ++i)
tc.setIntRegFlat(i, intRegs[i]);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 1e30649..e3a576b 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -95,11 +95,7 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
- typedef TheISA::MiscReg MiscReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
@@ -208,11 +204,11 @@
//
// New accessors for new decoder.
//
- virtual uint64_t readIntReg(int reg_idx) = 0;
+ virtual RegVal readIntReg(int reg_idx) = 0;

- virtual FloatReg readFloatReg(int reg_idx) = 0;
+ virtual FloatRegVal readFloatReg(int reg_idx) = 0;

- virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+ virtual RegVal readFloatRegBits(int reg_idx) = 0;

virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
@@ -250,11 +246,11 @@

virtual CCReg readCCReg(int reg_idx) = 0;

- virtual void setIntReg(int reg_idx, uint64_t val) = 0;
+ virtual void setIntReg(int reg_idx, RegVal val) = 0;

- virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
+ virtual void setFloatReg(int reg_idx, FloatRegVal val) = 0;

- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+ virtual void setFloatRegBits(int reg_idx, RegVal val) = 0;

virtual void setVecReg(const RegId& reg, const VecRegContainer& val) =
0;

@@ -282,24 +278,24 @@

virtual MicroPC microPC() = 0;

- virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
+ virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0;

- virtual MiscReg readMiscReg(int misc_reg) = 0;
+ virtual RegVal readMiscReg(int misc_reg) = 0;

- virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;

- virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;

virtual RegId flattenRegId(const RegId& regId) const = 0;

- virtual uint64_t
+ virtual RegVal
readRegOtherThread(const RegId& misc_reg, ThreadID tid)
{
return 0;
}

virtual void
- setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID
tid)
+ setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID
tid)
{
}

@@ -334,14 +330,14 @@
* serialization code to access all registers.
*/

- virtual uint64_t readIntRegFlat(int idx) = 0;
- virtual void setIntRegFlat(int idx, uint64_t val) = 0;
+ virtual RegVal readIntRegFlat(int idx) = 0;
+ virtual void setIntRegFlat(int idx, RegVal val) = 0;

- virtual FloatReg readFloatRegFlat(int idx) = 0;
- virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
+ virtual FloatRegVal readFloatRegFlat(int idx) = 0;
+ virtual void setFloatRegFlat(int idx, FloatRegVal val) = 0;

- virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
- virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
+ virtual RegVal readFloatRegBitsFlat(int idx) = 0;
+ virtual void setFloatRegBitsFlat(int idx, RegVal val) = 0;

virtual const VecRegContainer& readVecRegFlat(int idx) const = 0;
virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0;
@@ -461,13 +457,13 @@
//
// New accessors for new decoder.
//
- uint64_t readIntReg(int reg_idx)
+ RegVal readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }

- FloatReg readFloatReg(int reg_idx)
+ FloatRegVal readFloatReg(int reg_idx)
{ return actualTC->readFloatReg(reg_idx); }

- FloatRegBits readFloatRegBits(int reg_idx)
+ RegVal readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }

const VecRegContainer& readVecReg(const RegId& reg) const
@@ -519,13 +515,13 @@
CCReg readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }

- void setIntReg(int reg_idx, uint64_t val)
+ void setIntReg(int reg_idx, RegVal val)
{ actualTC->setIntReg(reg_idx, val); }

- void setFloatReg(int reg_idx, FloatReg val)
+ void setFloatReg(int reg_idx, FloatRegVal val)
{ actualTC->setFloatReg(reg_idx, val); }

- void setFloatRegBits(int reg_idx, FloatRegBits val)
+ void setFloatRegBits(int reg_idx, RegVal val)
{ actualTC->setFloatRegBits(reg_idx, val); }

void setVecReg(const RegId& reg, const VecRegContainer& val)
@@ -552,16 +548,16 @@
void setPredicate(bool val)
{ actualTC->setPredicate(val); }

- MiscReg readMiscRegNoEffect(int misc_reg) const
+ RegVal readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }

- MiscReg readMiscReg(int misc_reg)
+ RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }

- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const RegVal &val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }

- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const RegVal &val)
{ return actualTC->setMiscReg(misc_reg, val); }

RegId flattenRegId(const RegId& regId) const
@@ -578,22 +574,22 @@

Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }

- uint64_t readIntRegFlat(int idx)
+ RegVal readIntRegFlat(int idx)
{ return actualTC->readIntRegFlat(idx); }

- void setIntRegFlat(int idx, uint64_t val)
+ void setIntRegFlat(int idx, RegVal val)
{ actualTC->setIntRegFlat(idx, val); }

- FloatReg readFloatRegFlat(int idx)
+ FloatRegVal readFloatRegFlat(int idx)
{ return actualTC->readFloatRegFlat(idx); }

- void setFloatRegFlat(int idx, FloatReg val)
+ void setFloatRegFlat(int idx, FloatRegVal val)
{ actualTC->setFloatRegFlat(idx, val); }

- FloatRegBits readFloatRegBitsFlat(int idx)
+ RegVal readFloatRegBitsFlat(int idx)
{ return actualTC->readFloatRegBitsFlat(idx); }

- void setFloatRegBitsFlat(int idx, FloatRegBits val)
+ void setFloatRegBitsFlat(int idx, RegVal val)
{ actualTC->setFloatRegBitsFlat(idx, val); }

const VecRegContainer& readVecRegFlat(int id) const
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 0994f6d..396926f 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -312,7 +312,7 @@


void
-GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
+GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val)
{
CoreTimers &core(getTimers(cpu));

@@ -417,7 +417,7 @@
}


-MiscReg
+RegVal
GenericTimer::readMiscReg(int reg, unsigned cpu)
{
CoreTimers &core(getTimers(cpu));
@@ -508,16 +508,16 @@


void
-GenericTimerISA::setMiscReg(int reg, MiscReg val)
+GenericTimerISA::setMiscReg(int reg, RegVal val)
{
DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
parent.setMiscReg(reg, cpu, val);
}

-MiscReg
+RegVal
GenericTimerISA::readMiscReg(int reg)
{
- MiscReg value = parent.readMiscReg(reg, cpu);
+ RegVal value = parent.readMiscReg(reg, cpu);
DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
return value;
}
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index b3a7e76..acd8b39 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -223,8 +223,8 @@
void unserialize(CheckpointIn &cp) override;

public:
- void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
- ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu);
+ void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
+ RegVal readMiscReg(int misc_reg, unsigned cpu);

protected:
struct CoreTimers {
@@ -286,8 +286,8 @@
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
: parent(_parent), cpu(_cpu) {}

- void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
- ArmISA::MiscReg readMiscReg(int misc_reg) override;
+ void setMiscReg(int misc_reg, RegVal val) override;
+ RegVal readMiscReg(int misc_reg) override;

protected:
GenericTimer &parent;
diff --git a/src/gpu-compute/gpu_exec_context.cc
b/src/gpu-compute/gpu_exec_context.cc
index 0132397..76854f3 100644
--- a/src/gpu-compute/gpu_exec_context.cc
+++ b/src/gpu-compute/gpu_exec_context.cc
@@ -53,7 +53,7 @@
return wf;
}

-TheGpuISA::MiscReg
+RegVal
GPUExecContext::readMiscReg(int opIdx) const
{
assert(gpuISA);
@@ -61,7 +61,7 @@
}

void
-GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal)
+GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal)
{
assert(gpuISA);
gpuISA->writeMiscReg(opIdx, operandVal);
diff --git a/src/gpu-compute/gpu_exec_context.hh
b/src/gpu-compute/gpu_exec_context.hh
index c5f9929..327cf0b 100644
--- a/src/gpu-compute/gpu_exec_context.hh
+++ b/src/gpu-compute/gpu_exec_context.hh
@@ -49,8 +49,8 @@
Wavefront* wavefront();
ComputeUnit* computeUnit();

- TheGpuISA::MiscReg readMiscReg(int opIdx) const;
- void writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal);
+ RegVal readMiscReg(int opIdx) const;
+ void writeMiscReg(int opIdx, RegVal operandVal);

protected:
ComputeUnit *cu;
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index fea6183..db75efe 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -616,7 +616,7 @@
//The index is multiplied by the size of a MiscReg so that
//any memory dependence calculations will not see these as
//overlapping.
- req->setPaddr(regNum * sizeof(MiscReg));
+ req->setPaddr(regNum * sizeof(RegVal));
return NoFault;
} else if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O
permission
@@ -629,7 +629,7 @@

if (IOPort == 0xCF8 && req->getSize() == 4) {
req->setFlags(Request::MMAPPED_IPR);
- req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS *
sizeof(MiscReg));
+ req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE);

diff --git a/src/sim/process.cc b/src/sim/process.cc
index 5e9c2b5..62959b4 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -156,7 +156,7 @@

void
Process::clone(ThreadContext *otc, ThreadContext *ntc,
- Process *np, TheISA::IntReg flags)
+ Process *np, RegVal flags)
{
#ifndef CLONE_VM
#define CLONE_VM 0
@@ -423,7 +423,7 @@
desc->doSyscall(callnum, this, tc, fault);
}

-IntReg
+RegVal
Process::getSyscallArg(ThreadContext *tc, int &i, int width)
{
return getSyscallArg(tc, i);
diff --git a/src/sim/process.hh b/src/sim/process.hh
index cb2a3e2..c690e82 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -73,10 +73,9 @@
DrainState drain() override;

virtual void syscall(int64_t callnum, ThreadContext *tc, Fault *fault);
- virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i) = 0;
- virtual TheISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int
width);
- virtual void setSyscallArg(ThreadContext *tc, int i,
- TheISA::IntReg val) = 0;
+ virtual RegVal getSyscallArg(ThreadContext *tc, int &i) = 0;
+ virtual RegVal getSyscallArg(ThreadContext *tc, int &i, int width);
+ virtual void setSyscallArg(ThreadContext *tc, int i, RegVal val) = 0;
virtual void setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value) = 0;
virtual SyscallDesc *getDesc(int callnum) = 0;
@@ -163,7 +162,7 @@
ThreadContext *new_tc, bool alloc_page);

virtual void clone(ThreadContext *old_tc, ThreadContext *new_tc,
- Process *new_p, TheISA::IntReg flags);
+ Process *new_p, RegVal flags);

// thread contexts associated with this process
std::vector<ContextID> contextIds;
diff --git a/src/sim/syscall_desc.cc b/src/sim/syscall_desc.cc
index 3696c17..841998d 100644
--- a/src/sim/syscall_desc.cc
+++ b/src/sim/syscall_desc.cc
@@ -49,7 +49,7 @@
SyscallDesc::doSyscall(int callnum, Process *process, ThreadContext *tc,
Fault *fault)
{
- TheISA::IntReg arg[6] M5_VAR_USED;
+ RegVal arg[6] M5_VAR_USED;

/**
* Step through the first six parameters for the system call and
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index c7818b6..493d379 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1267,8 +1267,8 @@
{
int index = 0;

- TheISA::IntReg flags = p->getSyscallArg(tc, index);
- TheISA::IntReg newStack = p->getSyscallArg(tc, index);
+ RegVal flags = p->getSyscallArg(tc, index);
+ RegVal newStack = p->getSyscallArg(tc, index);
Addr ptidPtr = p->getSyscallArg(tc, index);

#if THE_ISA == RISCV_ISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Gerrit-Change-Number: 13624
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-MessageType: newchange
Gabe Black (Gerrit)
2018-11-06 01:16:51 UTC
Permalink
Hello Anthony Gutierrez, Jason Lowe-Power, Alec Roelke, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13624

to look at the new patch set (#2).

Change subject: cpu: dev: sim: gpu-compute: Banish some ISA specific
register types.
......................................................................

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_tlb.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_emul.hh
25 files changed, 546 insertions(+), 444 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13624
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https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Gerrit-Change-Number: 13624
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-MessageType: newpatchset
Gabe Black (Gerrit)
2018-11-20 03:30:44 UTC
Permalink
Hello Anthony Gutierrez, Jason Lowe-Power, Alec Roelke, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13624

to look at the new patch set (#3).

Change subject: cpu: dev: sim: gpu-compute: Banish some ISA specific
register types.
......................................................................

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_tlb.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_emul.hh
25 files changed, 476 insertions(+), 389 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13624
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Gerrit-Change-Number: 13624
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-CC: Bradford Beckmann <***@amd.com>
Gerrit-MessageType: newpatchset
Gabe Black (Gerrit)
2018-11-27 03:12:23 UTC
Permalink
Hello Anthony Gutierrez, Jason Lowe-Power, Alec Roelke, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/13624

to look at the new patch set (#5).

Change subject: cpu: dev: sim: gpu-compute: Banish some ISA specific
register types.
......................................................................

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
---
M src/arch/hsail/gpu_isa.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
M src/gpu-compute/gpu_exec_context.cc
M src/gpu-compute/gpu_exec_context.hh
M src/gpu-compute/gpu_tlb.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_desc.cc
M src/sim/syscall_emul.hh
26 files changed, 478 insertions(+), 389 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13624
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Gerrit-Change-Number: 13624
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-Reviewer: Alec Roelke <***@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <***@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <***@amd.com>
Gerrit-Reviewer: Gabe Black <***@google.com>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-CC: Bradford Beckmann <***@amd.com>
Gerrit-MessageType: newpatchset
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