Discussion:
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add parameter for tag-only access
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Daniel Carvalho (Gerrit)
2018-11-29 15:15:17 UTC
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Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14717


Change subject: mem-cache: Add parameter for tag-only access
......................................................................

mem-cache: Add parameter for tag-only access

Invalidations, cleans, updates and failed StoreCond do not
need to access the data array, and as such create the
opportunity of faster accesses that only take into account
tag lookup latency.

Change-Id: I100050dc7a452267d827662363ce80c3802ab225
Signed-off-by: Daniel R. Carvalho <***@yahoo.com.br>
---
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
3 files changed, 17 insertions(+), 3 deletions(-)



diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 8ffab91..4bfbd76 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -106,6 +106,8 @@

sequential_access = Param.Bool(False,
"Whether to access tags and data sequentially")
+ enable_tag_only_access = Param.Bool(True,
+ "Enable accesses that only affect the tag to not touch the data
array")

cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
mem_side = MasterPort("Downstream port closer to memory")
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index e4f6dc0..641f1f5 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -96,6 +96,7 @@
fillLatency(p->data_latency),
responseLatency(p->response_latency),
sequentialAccess(p->sequential_access),
+ tagOnlyAccesses(p->enable_tag_only_access),
numTarget(p->tgts_per_mshr),
forwardSnoops(true),
clusivity(p->clusivity),
@@ -914,12 +915,16 @@
const bool is_read,
const bool is_write) const
{
- Cycles lat(lookup_lat);
+ Cycles lat(0);

- if (blk != nullptr) {
+ // If access is a miss, or there is no data array access, only take
into
+ // account the tag lookup latency for the access latency
+ if ((blk == nullptr) || (tagOnlyAccesses && !(is_read || is_write))) {
+ lat = lookup_lat;
+ } else {
// First access tags, then data
if (sequentialAccess) {
- lat += dataLatency;
+ lat = lookup_lat + dataLatency;
// Latency is dictated by the slowest of tag and data latencies
} else {
lat = std::max(lookup_lat, dataLatency);
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index cfa7999..8b4d993 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -830,6 +830,13 @@
*/
const bool sequentialAccess;

+ /**
+ * Whether accesses must touch the data array, even if they do not
need to
+ * touch it, as is the case of invalidations, cleans, updates and
failed
+ * StoreCond.
+ */
+ const bool tagOnlyAccesses;
+
/** The number of targets for each MSHR. */
const int numTarget;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I100050dc7a452267d827662363ce80c3802ab225
Gerrit-Change-Number: 14717
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <***@yahoo.com.br>
Gerrit-MessageType: newchange
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