Gabe Black (Gerrit)
2018-11-22 00:24:00 UTC
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14515
Change subject: cpu, arch: Replace the CCReg type with RegVal.
......................................................................
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
---
M src/arch/alpha/registers.hh
M src/arch/arm/registers.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
23 files changed, 56 insertions(+), 77 deletions(-)
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 99962b5..092e113 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -45,9 +45,6 @@
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 8346f45..e72a93b 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -66,9 +66,6 @@
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 95373bb..66fa606 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -278,9 +278,6 @@
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 2101c82..5764491 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -46,7 +46,6 @@
namespace NullISA {
-typedef uint8_t CCReg;
const RegIndex ZeroReg = 0;
// dummy typedefs since we don't have vector regs
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index f96f8fb..01b8604 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -45,9 +45,6 @@
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index fa0614a..65e8018 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -63,8 +63,6 @@
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
-typedef uint8_t CCReg; // Not applicable to Riscv
-
// dummy typedefs since we don't have vector regs
const unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 5f12b98..9783678 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -45,9 +45,6 @@
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 6b1a8e8..429e964 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -90,8 +90,6 @@
// value
const int SyscallPseudoReturnReg = INTREG_RDX;
-typedef uint64_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index c2a1408..8042ebb 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -655,7 +655,7 @@
}
/** Records a CC register being set to a value. */
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 0721f44..553f53b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -304,7 +304,7 @@
return thread->readVecElem(reg);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -355,7 +355,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index b34b15d..9cd9345 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -263,7 +263,7 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void
@@ -295,7 +295,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
@@ -428,10 +428,10 @@
const ElemIndex& elem_idx, const VecElem& val)
{ actualTC->setVecElemFlat(idx, elem_idx, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 75f428b..ee0b001 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -74,7 +74,6 @@
public:
typedef TheISA::PCState PCState;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -172,8 +171,9 @@
* @{
* @name Condition Code Registers
*/
- virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
- virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
= 0;
+ virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setCCRegOperand(
+ const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/**
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4668018..310954c 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -376,7 +376,7 @@
thread.getDTBPtr()->demapPage(vaddr, asn);
}
- TheISA::CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -385,7 +385,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 5fc61a5..24aba3a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1316,7 +1316,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
ccRegfileReads++;
@@ -1357,7 +1357,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
ccRegfileWrites++;
regFile.setCCReg(phys_reg, val);
@@ -1416,7 +1416,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
ccRegfileReads++;
@@ -1470,7 +1470,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
+FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1a525fe..fd02d81 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -441,7 +441,7 @@
const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
- TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
+ RegVal readCCReg(PhysRegIdPtr phys_reg);
void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
@@ -451,7 +451,7 @@
void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
- void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
+ void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
RegVal readArchIntReg(int reg_idx, ThreadID tid);
@@ -485,7 +485,7 @@
const VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid)
const;
- TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+ RegVal readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -501,7 +501,7 @@
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid);
- void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+ void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6742995..a974708 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,7 +66,6 @@
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;
@@ -361,7 +360,8 @@
return this->cpu->readVecElem(this->_srcRegIdx[idx]);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readCCRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readCCReg(this->_srcRegIdx[idx]);
}
@@ -399,7 +399,7 @@
BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 9aa1dc2..ba71460 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,7 +65,6 @@
{
private:
- typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
@@ -90,7 +89,7 @@
std::vector<PhysRegId> vecElemIds;
/** Condition-code register file. */
- std::vector<CCReg> ccRegFile;
+ std::vector<RegVal> ccRegFile;
std::vector<PhysRegId> ccRegIds;
/** Misc Reg Ids */
@@ -259,7 +258,7 @@
}
/** Reads a condition-code register. */
- CCReg
+ RegVal
readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
@@ -323,7 +322,7 @@
/** Sets a condition-code register to the given value. */
void
- setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+ setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isCCPhysReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index a4d1924..26c47d6 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -263,7 +263,9 @@
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
}
- virtual CCReg readCCReg(int reg_idx) {
+ virtual RegVal
+ readCCReg(int reg_idx)
+ {
return readCCRegFlat(flattenRegId(RegId(CCRegClass,
reg_idx)).index());
}
@@ -295,7 +297,7 @@
}
virtual void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(),
val);
}
@@ -403,8 +405,8 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val);
- virtual CCReg readCCRegFlat(int idx);
- virtual void setCCRegFlat(int idx, CCReg val);
+ virtual RegVal readCCRegFlat(int idx);
+ virtual void setCCRegFlat(int idx, RegVal val);
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index 44772d0..d4b82d0 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -229,7 +229,7 @@
}
template <class Impl>
-TheISA::CCReg
+RegVal
O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
{
return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -273,7 +273,7 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
{
cpu->setArchCCReg(reg_idx, val, thread->threadId());
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 5d0a580..5c6b8c2 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -60,7 +60,6 @@
class SimpleExecContext : public ExecContext {
protected:
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -333,7 +332,7 @@
thread->setVecElem(reg, val);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
@@ -343,7 +342,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 46896db..5ad41bc 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -99,7 +99,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
@@ -110,7 +109,7 @@
RegVal intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
#ifdef ISA_HAS_CC_REGS
- TheISA::CCReg ccRegs[TheISA::NumCCRegs];
+ RegVal ccRegs[TheISA::NumCCRegs];
#endif
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -351,7 +350,8 @@
}
- CCReg readCCReg(int reg_idx)
+ RegVal
+ readCCReg(int reg_idx)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -411,7 +411,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -569,13 +569,13 @@
}
#ifdef ISA_HAS_CC_REGS
- CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
- void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
+ RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
+ void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
#else
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ panic("readCCRegFlat w/no CC regs!\n"); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ panic("setCCRegFlat w/no CC regs!\n"); }
#endif
};
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 06b58f7..8648922 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -96,8 +96,8 @@
// loop through the Condition Code registers.
for (int i = 0; i < TheISA::NumCCRegs; ++i) {
- TheISA::CCReg t1 = one->readCCReg(i);
- TheISA::CCReg t2 = two->readCCReg(i);
+ RegVal t1 = one->readCCReg(i);
+ RegVal t2 = two->readCCReg(i);
if (t1 != t2)
panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -174,7 +174,7 @@
SERIALIZE_ARRAY(intRegs, NumIntRegs);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
for (int i = 0; i < NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -209,7 +209,7 @@
tc.setIntRegFlat(i, intRegs[i]);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
for (int i = 0; i < NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9fe74b0..91c4a77 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -95,7 +95,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
@@ -242,7 +241,7 @@
virtual const VecElem& readVecElem(const RegId& reg) const = 0;
- virtual CCReg readCCReg(int reg_idx) = 0;
+ virtual RegVal readCCReg(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, RegVal val) = 0;
@@ -252,7 +251,7 @@
virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
- virtual void setCCReg(int reg_idx, CCReg val) = 0;
+ virtual void setCCReg(int reg_idx, RegVal val) = 0;
virtual TheISA::PCState pcState() = 0;
@@ -341,8 +340,8 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val) = 0;
- virtual CCReg readCCRegFlat(int idx) = 0;
- virtual void setCCRegFlat(int idx, CCReg val) = 0;
+ virtual RegVal readCCRegFlat(int idx) = 0;
+ virtual void setCCRegFlat(int idx, RegVal val) = 0;
/** @} */
};
@@ -502,7 +501,7 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void setIntReg(int reg_idx, RegVal val)
@@ -517,7 +516,7 @@
void setVecElem(const RegId& reg, const VecElem& val)
{ actualTC->setVecElem(reg, val); }
- void setCCReg(int reg_idx, CCReg val)
+ void setCCReg(int reg_idx, RegVal val)
{ actualTC->setCCReg(reg_idx, val); }
TheISA::PCState pcState() { return actualTC->pcState(); }
@@ -590,10 +589,10 @@
const VecElem& val)
{ actualTC->setVecElemFlat(id, elemIndex, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Gerrit-Change-Number: 14515
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <***@google.com>
Gerrit-MessageType: newchange
https://gem5-review.googlesource.com/c/public/gem5/+/14515
Change subject: cpu, arch: Replace the CCReg type with RegVal.
......................................................................
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
---
M src/arch/alpha/registers.hh
M src/arch/arm/registers.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
23 files changed, 56 insertions(+), 77 deletions(-)
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 99962b5..092e113 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -45,9 +45,6 @@
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 8346f45..e72a93b 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -66,9 +66,6 @@
using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
using VecRegContainer = VecReg::Container;
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 95373bb..66fa606 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -278,9 +278,6 @@
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 2101c82..5764491 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -46,7 +46,6 @@
namespace NullISA {
-typedef uint8_t CCReg;
const RegIndex ZeroReg = 0;
// dummy typedefs since we don't have vector regs
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index f96f8fb..01b8604 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -45,9 +45,6 @@
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index fa0614a..65e8018 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -63,8 +63,6 @@
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
-typedef uint8_t CCReg; // Not applicable to Riscv
-
// dummy typedefs since we don't have vector regs
const unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 5f12b98..9783678 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -45,9 +45,6 @@
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 6b1a8e8..429e964 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -90,8 +90,6 @@
// value
const int SyscallPseudoReturnReg = INTREG_RDX;
-typedef uint64_t CCReg;
-
// dummy typedefs since we don't have vector regs
constexpr unsigned NumVecElemPerVecReg = 2;
using VecElem = uint32_t;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index c2a1408..8042ebb 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -655,7 +655,7 @@
}
/** Records a CC register being set to a value. */
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 0721f44..553f53b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -304,7 +304,7 @@
return thread->readVecElem(reg);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -355,7 +355,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index b34b15d..9cd9345 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -263,7 +263,7 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void
@@ -295,7 +295,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
@@ -428,10 +428,10 @@
const ElemIndex& elem_idx, const VecElem& val)
{ actualTC->setVecElemFlat(idx, elem_idx, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 75f428b..ee0b001 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -74,7 +74,6 @@
public:
typedef TheISA::PCState PCState;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -172,8 +171,9 @@
* @{
* @name Condition Code Registers
*/
- virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
- virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
= 0;
+ virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
+ virtual void setCCRegOperand(
+ const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/**
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4668018..310954c 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -376,7 +376,7 @@
thread.getDTBPtr()->demapPage(vaddr, asn);
}
- TheISA::CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -385,7 +385,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 5fc61a5..24aba3a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1316,7 +1316,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
ccRegfileReads++;
@@ -1357,7 +1357,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
ccRegfileWrites++;
regFile.setCCReg(phys_reg, val);
@@ -1416,7 +1416,7 @@
}
template <class Impl>
-CCReg
+RegVal
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
ccRegfileReads++;
@@ -1470,7 +1470,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
+FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1a525fe..fd02d81 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -441,7 +441,7 @@
const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
- TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
+ RegVal readCCReg(PhysRegIdPtr phys_reg);
void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
@@ -451,7 +451,7 @@
void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
- void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
+ void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
RegVal readArchIntReg(int reg_idx, ThreadID tid);
@@ -485,7 +485,7 @@
const VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid)
const;
- TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+ RegVal readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -501,7 +501,7 @@
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid);
- void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+ void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6742995..a974708 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,7 +66,6 @@
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg =
TheISA::NumVecElemPerVecReg;
@@ -361,7 +360,8 @@
return this->cpu->readVecElem(this->_srcRegIdx[idx]);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ RegVal
+ readCCRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readCCReg(this->_srcRegIdx[idx]);
}
@@ -399,7 +399,7 @@
BaseDynInst<Impl>::setVecElemOperand(si, idx, val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 9aa1dc2..ba71460 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,7 +65,6 @@
{
private:
- typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
@@ -90,7 +89,7 @@
std::vector<PhysRegId> vecElemIds;
/** Condition-code register file. */
- std::vector<CCReg> ccRegFile;
+ std::vector<RegVal> ccRegFile;
std::vector<PhysRegId> ccRegIds;
/** Misc Reg Ids */
@@ -259,7 +258,7 @@
}
/** Reads a condition-code register. */
- CCReg
+ RegVal
readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
@@ -323,7 +322,7 @@
/** Sets a condition-code register to the given value. */
void
- setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+ setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isCCPhysReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index a4d1924..26c47d6 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -263,7 +263,9 @@
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
}
- virtual CCReg readCCReg(int reg_idx) {
+ virtual RegVal
+ readCCReg(int reg_idx)
+ {
return readCCRegFlat(flattenRegId(RegId(CCRegClass,
reg_idx)).index());
}
@@ -295,7 +297,7 @@
}
virtual void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(),
val);
}
@@ -403,8 +405,8 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val);
- virtual CCReg readCCRegFlat(int idx);
- virtual void setCCRegFlat(int idx, CCReg val);
+ virtual RegVal readCCRegFlat(int idx);
+ virtual void setCCRegFlat(int idx, RegVal val);
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index 44772d0..d4b82d0 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -229,7 +229,7 @@
}
template <class Impl>
-TheISA::CCReg
+RegVal
O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
{
return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -273,7 +273,7 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
{
cpu->setArchCCReg(reg_idx, val, thread->threadId());
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 5d0a580..5c6b8c2 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -60,7 +60,6 @@
class SimpleExecContext : public ExecContext {
protected:
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -333,7 +332,7 @@
thread->setVecElem(reg, val);
}
- CCReg
+ RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
@@ -343,7 +342,7 @@
}
void
- setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 46896db..5ad41bc 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -99,7 +99,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
@@ -110,7 +109,7 @@
RegVal intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
#ifdef ISA_HAS_CC_REGS
- TheISA::CCReg ccRegs[TheISA::NumCCRegs];
+ RegVal ccRegs[TheISA::NumCCRegs];
#endif
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -351,7 +350,8 @@
}
- CCReg readCCReg(int reg_idx)
+ RegVal
+ readCCReg(int reg_idx)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -411,7 +411,7 @@
}
void
- setCCReg(int reg_idx, CCReg val)
+ setCCReg(int reg_idx, RegVal val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -569,13 +569,13 @@
}
#ifdef ISA_HAS_CC_REGS
- CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
- void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
+ RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
+ void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
#else
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ panic("readCCRegFlat w/no CC regs!\n"); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ panic("setCCRegFlat w/no CC regs!\n"); }
#endif
};
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 06b58f7..8648922 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -96,8 +96,8 @@
// loop through the Condition Code registers.
for (int i = 0; i < TheISA::NumCCRegs; ++i) {
- TheISA::CCReg t1 = one->readCCReg(i);
- TheISA::CCReg t2 = two->readCCReg(i);
+ RegVal t1 = one->readCCReg(i);
+ RegVal t2 = two->readCCReg(i);
if (t1 != t2)
panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -174,7 +174,7 @@
SERIALIZE_ARRAY(intRegs, NumIntRegs);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
for (int i = 0; i < NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -209,7 +209,7 @@
tc.setIntRegFlat(i, intRegs[i]);
#ifdef ISA_HAS_CC_REGS
- CCReg ccRegs[NumCCRegs];
+ RegVal ccRegs[NumCCRegs];
UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
for (int i = 0; i < NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9fe74b0..91c4a77 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -95,7 +95,6 @@
{
protected:
typedef TheISA::MachInst MachInst;
- typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
public:
@@ -242,7 +241,7 @@
virtual const VecElem& readVecElem(const RegId& reg) const = 0;
- virtual CCReg readCCReg(int reg_idx) = 0;
+ virtual RegVal readCCReg(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, RegVal val) = 0;
@@ -252,7 +251,7 @@
virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
- virtual void setCCReg(int reg_idx, CCReg val) = 0;
+ virtual void setCCReg(int reg_idx, RegVal val) = 0;
virtual TheISA::PCState pcState() = 0;
@@ -341,8 +340,8 @@
virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex&
elemIdx,
const VecElem& val) = 0;
- virtual CCReg readCCRegFlat(int idx) = 0;
- virtual void setCCRegFlat(int idx, CCReg val) = 0;
+ virtual RegVal readCCRegFlat(int idx) = 0;
+ virtual void setCCRegFlat(int idx, RegVal val) = 0;
/** @} */
};
@@ -502,7 +501,7 @@
const VecElem& readVecElem(const RegId& reg) const
{ return actualTC->readVecElem(reg); }
- CCReg readCCReg(int reg_idx)
+ RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void setIntReg(int reg_idx, RegVal val)
@@ -517,7 +516,7 @@
void setVecElem(const RegId& reg, const VecElem& val)
{ actualTC->setVecElem(reg, val); }
- void setCCReg(int reg_idx, CCReg val)
+ void setCCReg(int reg_idx, RegVal val)
{ actualTC->setCCReg(reg_idx, val); }
TheISA::PCState pcState() { return actualTC->pcState(); }
@@ -590,10 +589,10 @@
const VecElem& val)
{ actualTC->setVecElemFlat(id, elemIndex, val); }
- CCReg readCCRegFlat(int idx)
+ RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
- void setCCRegFlat(int idx, CCReg val)
+ void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};
--
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