Discussion:
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix include directives in the cache related classes
(too old to reply)
Nikos Nikoleris (Gerrit)
2018-05-11 10:30:15 UTC
Permalink
Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/10433


Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
42 files changed, 171 insertions(+), 42 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a2588e2..8c33bf4 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -48,12 +48,19 @@

#include "mem/cache/base.hh"

+#include "base/compiler.hh"
+#include "base/logging.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "debug/CacheVerbose.hh"
-#include "debug/Drain.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/prefetch/base.hh"
+#include "mem/cache/queue_entry.hh"
+#include "params/BaseCache.hh"
+#include "sim/core.hh"
+
+class BaseMasterPort;
+class BaseSlavePort;

using namespace std;

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 758f726..f6fe132 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -52,12 +52,11 @@
#ifndef __MEM_CACHE_BASE_HH__
#define __MEM_CACHE_BASE_HH__

-#include <algorithm>
-#include <list>
+#include <cassert>
+#include <cstdint>
#include <string>
-#include <vector>

-#include "base/logging.hh"
+#include "base/addr_range.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
@@ -68,16 +67,25 @@
#include "mem/cache/mshr_queue.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/write_queue.hh"
+#include "mem/cache/write_queue_entry.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
+#include "mem/packet_queue.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
-#include "params/BaseCache.hh"
#include "sim/eventq.hh"
-#include "sim/full_system.hh"
+#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"

+class BaseMasterPort;
+class BasePrefetcher;
+class BaseSlavePort;
+class MSHR;
+class MasterPort;
+class QueueEntry;
+struct BaseCacheParams;
+
/**
* A basic cache interface. Implements some common functions for speed.
*/
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 561d502..951abd5 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -48,9 +48,14 @@
#ifndef __MEM_CACHE_BLK_HH__
#define __MEM_CACHE_BLK_HH__

+#include <cassert>
+#include <cstdint>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 0f9f781..38c7a65 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -54,16 +54,22 @@

#include "mem/cache/cache.hh"

+#include <cassert>
+
+#include "base/compiler.hh"
#include "base/logging.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
-#include "debug/CachePort.hh"
#include "debug/CacheTags.hh"
#include "debug/CacheVerbose.hh"
+#include "enums/Clusivity.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
-#include "mem/cache/prefetch/base.hh"
-#include "sim/sim_exit.hh"
+#include "mem/cache/tags/base.hh"
+#include "mem/cache/write_queue_entry.hh"
+#include "mem/request.hh"
+#include "params/Cache.hh"

Cache::Cache(const CacheParams *p)
: BaseCache(p, p->system->cacheLineSize()),
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 65dbf35..89e70cd 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -52,11 +52,16 @@
#ifndef __MEM_CACHE_CACHE_HH__
#define __MEM_CACHE_CACHE_HH__

+#include <cstdint>
#include <unordered_set>

-#include "base/logging.hh" // fatal, panic, and warn
+#include "base/types.hh"
#include "mem/cache/base.hh"
-#include "params/Cache.hh"
+#include "mem/packet.hh"
+
+class CacheBlk;
+struct CacheParams;
+class MSHR;

/**
* A coherent cache that can be arranged in flexible topologies.
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index afbbb90..bf9deaf 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -49,15 +49,15 @@

#include "mem/cache/mshr.hh"

-#include <algorithm>
#include <cassert>
#include <string>
-#include <vector>

#include "base/logging.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
+#include "mem/cache/base.hh"
+#include "mem/request.hh"
#include "sim/core.hh"

MSHR::MSHR() : downstreamPending(false),
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index d749ae2..9bbf4a2 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -48,10 +48,16 @@
#ifndef __MEM_CACHE_MSHR_HH__
#define __MEM_CACHE_MSHR_HH__

+#include <cassert>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"

class BaseCache;

diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 29358d7..e44a219 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -47,6 +47,10 @@

#include "mem/cache/mshr_queue.hh"

+#include <cassert>
+
+#include "mem/cache/mshr.hh"
+
MSHRQueue::MSHRQueue(const std::string &_label,
int num_entries, int reserve, int demand_reserve)
: Queue<MSHR>(_label, num_entries, reserve),
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index f0b5c2a..1b960a5 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -48,10 +48,12 @@
#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
#define __MEM_CACHE_MSHR_QUEUE_HH__

-#include <vector>
+#include <string>

+#include "base/types.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/queue.hh"
+#include "mem/packet.hh"

/**
* A Class for maintaining a list of pending and allocated memory requests.
diff --git a/src/mem/cache/noncoherent_cache.cc
b/src/mem/cache/noncoherent_cache.cc
index d8e4bcc..6b477df 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -54,16 +54,15 @@

#include "mem/cache/noncoherent_cache.hh"

+#include <cassert>
+
#include "base/logging.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
-#include "debug/CachePort.hh"
-#include "debug/CacheTags.hh"
-#include "debug/CacheVerbose.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
-#include "mem/cache/prefetch/base.hh"
-#include "sim/sim_exit.hh"
+#include "params/NoncoherentCache.hh"

NoncoherentCache::NoncoherentCache(const NoncoherentCacheParams *p)
: BaseCache(p, p->system->cacheLineSize())
diff --git a/src/mem/cache/noncoherent_cache.hh
b/src/mem/cache/noncoherent_cache.hh
index 064e7fa..38abac9 100644
--- a/src/mem/cache/noncoherent_cache.hh
+++ b/src/mem/cache/noncoherent_cache.hh
@@ -56,8 +56,14 @@
#ifndef __MEM_CACHE_NONCOHERENT_CACHE_HH__
#define __MEM_CACHE_NONCOHERENT_CACHE_HH__

+#include "base/logging.hh"
+#include "base/types.hh"
#include "mem/cache/base.hh"
-#include "params/NoncoherentCache.hh"
+#include "mem/packet.hh"
+
+class CacheBlk;
+class MSHR;
+struct NoncoherentCacheParams;

/**
* A non-coherent cache
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 90c6742..22a12ba 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -48,10 +48,11 @@

#include "mem/cache/prefetch/base.hh"

-#include <list>
+#include <cassert>

#include "base/intmath.hh"
#include "mem/cache/base.hh"
+#include "params/BasePrefetcher.hh"
#include "sim/system.hh"

BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 3b23106..cc54ab1 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -49,12 +49,17 @@
#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
#define __MEM_CACHE_PREFETCH_BASE_HH__

+#include <cstdint>
+
#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/packet.hh"
-#include "params/BasePrefetcher.hh"
+#include "mem/request.hh"
#include "sim/clocked_object.hh"

class BaseCache;
+struct BasePrefetcherParams;
+class System;

class BasePrefetcher : public ClockedObject
{
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 4a685d8..bf3a384 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -39,8 +39,13 @@

#include "mem/cache/prefetch/queued.hh"

+#include <cassert>
+
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
-#include "mem/cache/base.hh"
+#include "mem/request.hh"
+#include "params/QueuedPrefetcher.hh"

QueuedPrefetcher::QueuedPrefetcher(const QueuedPrefetcherParams *p)
: BasePrefetcher(p), queueSize(p->queue_size), latency(p->latency),
diff --git a/src/mem/cache/prefetch/queued.hh
b/src/mem/cache/prefetch/queued.hh
index 108891f..bb38377 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -40,10 +40,16 @@
#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
#define __MEM_CACHE_PREFETCH_QUEUED_HH__

+#include <cstdint>
#include <list>
+#include <utility>

+#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/prefetch/base.hh"
-#include "params/QueuedPrefetcher.hh"
+#include "mem/packet.hh"
+
+struct QueuedPrefetcherParams;

class QueuedPrefetcher : public BasePrefetcher
{
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index f2679a2..efe982a 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -48,9 +48,14 @@

#include "mem/cache/prefetch/stride.hh"

+#include <cassert>
+
+#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
+#include "params/StridePrefetcher.hh"

StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
: QueuedPrefetcher(p),
diff --git a/src/mem/cache/prefetch/stride.hh
b/src/mem/cache/prefetch/stride.hh
index be6e41d..55cdbc8 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -48,10 +48,14 @@
#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_HH__

+#include <string>
#include <unordered_map>

+#include "base/types.hh"
#include "mem/cache/prefetch/queued.hh"
-#include "params/StridePrefetcher.hh"
+#include "mem/packet.hh"
+
+struct StridePrefetcherParams;

class StridePrefetcher : public QueuedPrefetcher
{
diff --git a/src/mem/cache/prefetch/tagged.cc
b/src/mem/cache/prefetch/tagged.cc
index 32a5b47..abe6b9d 100644
--- a/src/mem/cache/prefetch/tagged.cc
+++ b/src/mem/cache/prefetch/tagged.cc
@@ -35,6 +35,8 @@

#include "mem/cache/prefetch/tagged.hh"

+#include "params/TaggedPrefetcher.hh"
+
TaggedPrefetcher::TaggedPrefetcher(const TaggedPrefetcherParams *p)
: QueuedPrefetcher(p), degree(p->degree)
{
diff --git a/src/mem/cache/prefetch/tagged.hh
b/src/mem/cache/prefetch/tagged.hh
index 02debe9..95162aa 100644
--- a/src/mem/cache/prefetch/tagged.hh
+++ b/src/mem/cache/prefetch/tagged.hh
@@ -37,8 +37,9 @@
#define __MEM_CACHE_PREFETCH_TAGGED_HH__

#include "mem/cache/prefetch/queued.hh"
-#include "params/TaggedPrefetcher.hh"
+#include "mem/packet.hh"

+struct TaggedPrefetcherParams;

class TaggedPrefetcher : public QueuedPrefetcher
{
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index f603ea8..8e5ccf1 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -50,10 +50,14 @@
#define __MEM_CACHE_QUEUE_HH__

#include <cassert>
+#include <string>

#include "base/trace.hh"
+#include "base/types.hh"
#include "debug/Drain.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"
#include "sim/drain.hh"

/**
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 8923d86..7ab9e4f 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -49,6 +49,7 @@
#ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
#define __MEM_CACHE_QUEUE_ENTRY_HH__

+#include "base/types.hh"
#include "mem/packet.hh"

class BaseCache;
diff --git a/src/mem/cache/replacement_policies/brrip_rp.cc
b/src/mem/cache/replacement_policies/brrip_rp.cc
index 846b4fb..19a10f8 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.cc
+++ b/src/mem/cache/replacement_policies/brrip_rp.cc
@@ -30,6 +30,7 @@

#include "mem/cache/replacement_policies/brrip_rp.hh"

+#include <cassert>
#include <memory>

#include "base/logging.hh" // For fatal_if
diff --git a/src/mem/cache/replacement_policies/fifo_rp.cc
b/src/mem/cache/replacement_policies/fifo_rp.cc
index 731945a..127c95e 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.cc
+++ b/src/mem/cache/replacement_policies/fifo_rp.cc
@@ -30,6 +30,7 @@

#include "mem/cache/replacement_policies/fifo_rp.hh"

+#include <cassert>
#include <memory>

FIFORP::FIFORP(const Params *p)
diff --git a/src/mem/cache/replacement_policies/fifo_rp.hh
b/src/mem/cache/replacement_policies/fifo_rp.hh
index 34067d5..7770302 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.hh
+++ b/src/mem/cache/replacement_policies/fifo_rp.hh
@@ -38,6 +38,7 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_FIFO_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_FIFO_RP_HH__

+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
#include "params/FIFORP.hh"

diff --git a/src/mem/cache/replacement_policies/lfu_rp.cc
b/src/mem/cache/replacement_policies/lfu_rp.cc
index ffa653e..84ecf2d 100644
--- a/src/mem/cache/replacement_policies/lfu_rp.cc
+++ b/src/mem/cache/replacement_policies/lfu_rp.cc
@@ -30,6 +30,7 @@

#include "mem/cache/replacement_policies/lfu_rp.hh"

+#include <cassert>
#include <memory>

LFURP::LFURP(const Params *p)
diff --git a/src/mem/cache/replacement_policies/lru_rp.cc
b/src/mem/cache/replacement_policies/lru_rp.cc
index 99e35db..9fab4a6 100644
--- a/src/mem/cache/replacement_policies/lru_rp.cc
+++ b/src/mem/cache/replacement_policies/lru_rp.cc
@@ -30,6 +30,7 @@

#include "mem/cache/replacement_policies/lru_rp.hh"

+#include <cassert>
#include <memory>

LRURP::LRURP(const Params *p)
diff --git a/src/mem/cache/replacement_policies/mru_rp.cc
b/src/mem/cache/replacement_policies/mru_rp.cc
index ff84fc3..b2e019f 100644
--- a/src/mem/cache/replacement_policies/mru_rp.cc
+++ b/src/mem/cache/replacement_policies/mru_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/mru_rp.hh"

+#include <cassert>
#include <memory>

+#include "params/MRURP.hh"
+
MRURP::MRURP(const Params *p)
: BaseReplacementPolicy(p)
{
diff --git a/src/mem/cache/replacement_policies/mru_rp.hh
b/src/mem/cache/replacement_policies/mru_rp.hh
index 11cc272..f7cfddc 100644
--- a/src/mem/cache/replacement_policies/mru_rp.hh
+++ b/src/mem/cache/replacement_policies/mru_rp.hh
@@ -38,8 +38,10 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_MRU_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_MRU_RP_HH__

+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
-#include "params/MRURP.hh"
+
+class MRURPParams;

class MRURP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/random_rp.cc
b/src/mem/cache/replacement_policies/random_rp.cc
index 24e64fc..b4649ef 100644
--- a/src/mem/cache/replacement_policies/random_rp.cc
+++ b/src/mem/cache/replacement_policies/random_rp.cc
@@ -30,8 +30,9 @@

#include "mem/cache/replacement_policies/random_rp.hh"

+#include <cassert>
+
#include "base/random.hh"
-#include "mem/cache/blk.hh"

RandomRP::RandomRP(const Params *p)
: BaseReplacementPolicy(p)
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.cc
b/src/mem/cache/replacement_policies/second_chance_rp.cc
index 2560a98..64e667f 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.cc
+++ b/src/mem/cache/replacement_policies/second_chance_rp.cc
@@ -30,6 +30,10 @@

#include "mem/cache/replacement_policies/second_chance_rp.hh"

+#include <cassert>
+
+#include "params/SecondChanceRP.hh"
+
SecondChanceRP::SecondChanceRP(const Params *p)
: FIFORP(p)
{
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.hh
b/src/mem/cache/replacement_policies/second_chance_rp.hh
index 5522d5e..225d1ad 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.hh
+++ b/src/mem/cache/replacement_policies/second_chance_rp.hh
@@ -40,8 +40,10 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_SECOND_CHANCE_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_SECOND_CHANCE_RP_HH__

+#include "mem/cache/replacement_policies/base.hh"
#include "mem/cache/replacement_policies/fifo_rp.hh"
-#include "params/SecondChanceRP.hh"
+
+class SecondChanceRPParams;

class SecondChanceRP : public FIFORP
{
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 7d0a939..c7ea17b 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -48,8 +48,15 @@

#include "mem/cache/tags/base.hh"

+#include <cassert>
+
+#include "base/types.hh"
#include "mem/cache/base.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "sim/core.hh"
#include "sim/sim_exit.hh"
+#include "sim/system.hh"

BaseTags::BaseTags(const Params *p)
: ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 31fbfc0..e162118 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -49,12 +49,15 @@
#ifndef __MEM_CACHE_TAGS_BASE_HH__
#define __MEM_CACHE_TAGS_BASE_HH__

+#include <cassert>
#include <string>

#include "base/callback.hh"
+#include "base/logging.hh"
#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/blk.hh"
-#include "mem/cache/replacement_policies/base.hh"
+#include "mem/packet.hh"
#include "params/BaseTags.hh"
#include "sim/clocked_object.hh"

diff --git a/src/mem/cache/tags/base_set_assoc.cc
b/src/mem/cache/tags/base_set_assoc.cc
index 5888d1f..d3420b4 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -47,9 +47,11 @@

#include "mem/cache/tags/base_set_assoc.hh"

+#include <cassert>
#include <string>

#include "base/intmath.hh"
+#include "mem/request.hh"

BaseSetAssoc::BaseSetAssoc(const Params *p)
:BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index 5a3e832..2aa3a74 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -48,10 +48,11 @@
#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__

-#include <cassert>
-#include <cstring>
#include <vector>
+#include <string>

+#include "base/logging.hh"
+#include "base/types.hh"
#include "debug/CacheRepl.hh"
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
diff --git a/src/mem/cache/tags/cacheset.hh b/src/mem/cache/tags/cacheset.hh
index 5a34456..2675d45 100644
--- a/src/mem/cache/tags/cacheset.hh
+++ b/src/mem/cache/tags/cacheset.hh
@@ -49,6 +49,9 @@
#define __MEM_CACHE_TAGS_CACHESET_HH__

#include <cassert>
+#include <vector>
+
+#include "base/types.hh"

/**
* An associative set of cache blocks.
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 6abae2b..29dab3b 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -53,6 +53,7 @@

#include "base/intmath.hh"
#include "base/logging.hh"
+#include "mem/cache/base.hh"

FALRU::FALRU(const Params *p)
: BaseTags(p),
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index bec98e3..98a6457 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -49,11 +49,15 @@
#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
#define __MEM_CACHE_TAGS_FA_LRU_HH__

-#include <list>
+#include <cstdint>
+#include <string>
#include <unordered_map>

+#include "base/bitfield.hh"
#include "base/intmath.hh"
-#include "mem/cache/base.hh"
+#include "base/logging.hh"
+#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/tags/base.hh"
#include "mem/packet.hh"
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index 13e0fc5..11a2620 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -48,6 +48,10 @@

#include "mem/cache/write_queue.hh"

+#include <cassert>
+
+#include "mem/cache/write_queue_entry.hh"
+
WriteQueue::WriteQueue(const std::string &_label,
int num_entries, int reserve)
: Queue<WriteQueueEntry>(_label, num_entries, reserve)
diff --git a/src/mem/cache/write_queue.hh b/src/mem/cache/write_queue.hh
index 006d705..d9ace0d 100644
--- a/src/mem/cache/write_queue.hh
+++ b/src/mem/cache/write_queue.hh
@@ -45,10 +45,12 @@
#ifndef __MEM_CACHE_WRITE_QUEUE_HH__
#define __MEM_CACHE_WRITE_QUEUE_HH__

-#include <vector>
+#include <string>

+#include "base/types.hh"
#include "mem/cache/queue.hh"
#include "mem/cache/write_queue_entry.hh"
+#include "mem/packet.hh"

/**
* A write queue for all eviction packets, i.e. writebacks and clean
diff --git a/src/mem/cache/write_queue_entry.cc
b/src/mem/cache/write_queue_entry.cc
index 4aa174b..e393731 100644
--- a/src/mem/cache/write_queue_entry.cc
+++ b/src/mem/cache/write_queue_entry.cc
@@ -50,16 +50,13 @@

#include "mem/cache/write_queue_entry.hh"

-#include <algorithm>
#include <cassert>
#include <string>
-#include <vector>

#include "base/logging.hh"
#include "base/types.hh"
-#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
-#include "sim/core.hh"
+#include "mem/cache/base.hh"
+#include "mem/request.hh"

inline void
WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
diff --git a/src/mem/cache/write_queue_entry.hh
b/src/mem/cache/write_queue_entry.hh
index 40079b4..5a4b5a8 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -49,10 +49,16 @@
#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__

+#include <cassert>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"

class BaseCache;
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: newchange
Nikos Nikoleris (Gerrit)
2018-05-14 13:39:20 UTC
Permalink
Hello Daniel Carvalho,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10433

to look at the new patch set (#2).

Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
39 files changed, 138 insertions(+), 28 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-Reviewer: Daniel Carvalho <***@yahoo.com.br>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: newpatchset
Nikos Nikoleris (Gerrit)
2018-05-15 15:10:14 UTC
Permalink
Hello Daniel Carvalho, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10433

to look at the new patch set (#3).

Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
41 files changed, 141 insertions(+), 29 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 3
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-Reviewer: Daniel Carvalho <***@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: newpatchset
Nikos Nikoleris (Gerrit)
2018-05-31 13:38:16 UTC
Permalink
Hello Daniel Carvalho, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10433

to look at the new patch set (#6).

Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
42 files changed, 144 insertions(+), 30 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 6
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-Reviewer: Daniel Carvalho <***@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: newpatchset
Nikos Nikoleris (Gerrit)
2018-05-31 15:40:30 UTC
Permalink
Hello Daniel Carvalho, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10433

to look at the new patch set (#7).

Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
42 files changed, 144 insertions(+), 30 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 7
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-Reviewer: Daniel Carvalho <***@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: newpatchset
Nikos Nikoleris (Gerrit)
2018-05-31 17:45:25 UTC
Permalink
Nikos Nikoleris has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10433 )

Change subject: mem-cache: Fix include directives in the cache related
classes
......................................................................

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <***@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <***@lowepower.com>
Maintainer: Nikos Nikoleris <***@arm.com>
---
M src/mem/cache/blk.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
42 files changed, 144 insertions(+), 30 deletions(-)

Approvals:
Jason Lowe-Power: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved



diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 561d502..951abd5 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -48,9 +48,14 @@
#ifndef __MEM_CACHE_BLK_HH__
#define __MEM_CACHE_BLK_HH__

+#include <cassert>
+#include <cstdint>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index f5b346e..dc49079 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -49,15 +49,15 @@

#include "mem/cache/mshr.hh"

-#include <algorithm>
#include <cassert>
#include <string>
-#include <vector>

#include "base/logging.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
+#include "mem/cache/base.hh"
+#include "mem/request.hh"
#include "sim/core.hh"

MSHR::MSHR() : downstreamPending(false),
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index c4c7640..5c5a9e8 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -48,10 +48,16 @@
#ifndef __MEM_CACHE_MSHR_HH__
#define __MEM_CACHE_MSHR_HH__

+#include <cassert>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"

class BaseCache;

diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 29358d7..e44a219 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -47,6 +47,10 @@

#include "mem/cache/mshr_queue.hh"

+#include <cassert>
+
+#include "mem/cache/mshr.hh"
+
MSHRQueue::MSHRQueue(const std::string &_label,
int num_entries, int reserve, int demand_reserve)
: Queue<MSHR>(_label, num_entries, reserve),
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index f0b5c2a..1b960a5 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -48,10 +48,12 @@
#ifndef __MEM_CACHE_MSHR_QUEUE_HH__
#define __MEM_CACHE_MSHR_QUEUE_HH__

-#include <vector>
+#include <string>

+#include "base/types.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/queue.hh"
+#include "mem/packet.hh"

/**
* A Class for maintaining a list of pending and allocated memory requests.
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 90c6742..22a12ba 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -48,10 +48,11 @@

#include "mem/cache/prefetch/base.hh"

-#include <list>
+#include <cassert>

#include "base/intmath.hh"
#include "mem/cache/base.hh"
+#include "params/BasePrefetcher.hh"
#include "sim/system.hh"

BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 3b23106..cc54ab1 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -49,12 +49,17 @@
#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
#define __MEM_CACHE_PREFETCH_BASE_HH__

+#include <cstdint>
+
#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/packet.hh"
-#include "params/BasePrefetcher.hh"
+#include "mem/request.hh"
#include "sim/clocked_object.hh"

class BaseCache;
+struct BasePrefetcherParams;
+class System;

class BasePrefetcher : public ClockedObject
{
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 4a685d8..bf3a384 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -39,8 +39,13 @@

#include "mem/cache/prefetch/queued.hh"

+#include <cassert>
+
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
-#include "mem/cache/base.hh"
+#include "mem/request.hh"
+#include "params/QueuedPrefetcher.hh"

QueuedPrefetcher::QueuedPrefetcher(const QueuedPrefetcherParams *p)
: BasePrefetcher(p), queueSize(p->queue_size), latency(p->latency),
diff --git a/src/mem/cache/prefetch/queued.hh
b/src/mem/cache/prefetch/queued.hh
index 108891f..bb38377 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -40,10 +40,16 @@
#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
#define __MEM_CACHE_PREFETCH_QUEUED_HH__

+#include <cstdint>
#include <list>
+#include <utility>

+#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/prefetch/base.hh"
-#include "params/QueuedPrefetcher.hh"
+#include "mem/packet.hh"
+
+struct QueuedPrefetcherParams;

class QueuedPrefetcher : public BasePrefetcher
{
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index f2679a2..efe982a 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -48,9 +48,14 @@

#include "mem/cache/prefetch/stride.hh"

+#include <cassert>
+
+#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
+#include "params/StridePrefetcher.hh"

StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
: QueuedPrefetcher(p),
diff --git a/src/mem/cache/prefetch/stride.hh
b/src/mem/cache/prefetch/stride.hh
index be6e41d..55cdbc8 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -48,10 +48,14 @@
#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_HH__

+#include <string>
#include <unordered_map>

+#include "base/types.hh"
#include "mem/cache/prefetch/queued.hh"
-#include "params/StridePrefetcher.hh"
+#include "mem/packet.hh"
+
+struct StridePrefetcherParams;

class StridePrefetcher : public QueuedPrefetcher
{
diff --git a/src/mem/cache/prefetch/tagged.cc
b/src/mem/cache/prefetch/tagged.cc
index 32a5b47..abe6b9d 100644
--- a/src/mem/cache/prefetch/tagged.cc
+++ b/src/mem/cache/prefetch/tagged.cc
@@ -35,6 +35,8 @@

#include "mem/cache/prefetch/tagged.hh"

+#include "params/TaggedPrefetcher.hh"
+
TaggedPrefetcher::TaggedPrefetcher(const TaggedPrefetcherParams *p)
: QueuedPrefetcher(p), degree(p->degree)
{
diff --git a/src/mem/cache/prefetch/tagged.hh
b/src/mem/cache/prefetch/tagged.hh
index 02debe9..95162aa 100644
--- a/src/mem/cache/prefetch/tagged.hh
+++ b/src/mem/cache/prefetch/tagged.hh
@@ -37,8 +37,9 @@
#define __MEM_CACHE_PREFETCH_TAGGED_HH__

#include "mem/cache/prefetch/queued.hh"
-#include "params/TaggedPrefetcher.hh"
+#include "mem/packet.hh"

+struct TaggedPrefetcherParams;

class TaggedPrefetcher : public QueuedPrefetcher
{
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index f603ea8..8e5ccf1 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -50,10 +50,14 @@
#define __MEM_CACHE_QUEUE_HH__

#include <cassert>
+#include <string>

#include "base/trace.hh"
+#include "base/types.hh"
#include "debug/Drain.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"
#include "sim/drain.hh"

/**
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 8923d86..7ab9e4f 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -49,6 +49,7 @@
#ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
#define __MEM_CACHE_QUEUE_ENTRY_HH__

+#include "base/types.hh"
#include "mem/packet.hh"

class BaseCache;
diff --git a/src/mem/cache/replacement_policies/bip_rp.cc
b/src/mem/cache/replacement_policies/bip_rp.cc
index 4a3a516..93143ca 100644
--- a/src/mem/cache/replacement_policies/bip_rp.cc
+++ b/src/mem/cache/replacement_policies/bip_rp.cc
@@ -33,6 +33,7 @@
#include <memory>

#include "base/random.hh"
+#include "params/BIPRP.hh"

BIPRP::BIPRP(const Params *p)
: LRURP(p), btp(p->btp)
diff --git a/src/mem/cache/replacement_policies/bip_rp.hh
b/src/mem/cache/replacement_policies/bip_rp.hh
index ac4db02..aa8df05 100644
--- a/src/mem/cache/replacement_policies/bip_rp.hh
+++ b/src/mem/cache/replacement_policies/bip_rp.hh
@@ -45,7 +45,8 @@
#define __MEM_CACHE_REPLACEMENT_POLICIES_BIP_RP_HH__

#include "mem/cache/replacement_policies/lru_rp.hh"
-#include "params/BIPRP.hh"
+
+struct BIPRPParams;

class BIPRP : public LRURP
{
diff --git a/src/mem/cache/replacement_policies/brrip_rp.cc
b/src/mem/cache/replacement_policies/brrip_rp.cc
index 846b4fb..dc41d8b 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.cc
+++ b/src/mem/cache/replacement_policies/brrip_rp.cc
@@ -30,10 +30,12 @@

#include "mem/cache/replacement_policies/brrip_rp.hh"

+#include <cassert>
#include <memory>

#include "base/logging.hh" // For fatal_if
#include "base/random.hh"
+#include "params/BRRIPRP.hh"

BRRIPRP::BRRIPRP(const Params *p)
: BaseReplacementPolicy(p),
diff --git a/src/mem/cache/replacement_policies/brrip_rp.hh
b/src/mem/cache/replacement_policies/brrip_rp.hh
index e442d85..9374742 100644
--- a/src/mem/cache/replacement_policies/brrip_rp.hh
+++ b/src/mem/cache/replacement_policies/brrip_rp.hh
@@ -55,7 +55,8 @@
#define __MEM_CACHE_REPLACEMENT_POLICIES_BRRIP_RP_HH__

#include "mem/cache/replacement_policies/base.hh"
-#include "params/BRRIPRP.hh"
+
+struct BRRIPRPParams;

class BRRIPRP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/fifo_rp.cc
b/src/mem/cache/replacement_policies/fifo_rp.cc
index 731945a..7c5ce02 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.cc
+++ b/src/mem/cache/replacement_policies/fifo_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/fifo_rp.hh"

+#include <cassert>
#include <memory>

+#include "params/FIFORP.hh"
+
FIFORP::FIFORP(const Params *p)
: BaseReplacementPolicy(p)
{
diff --git a/src/mem/cache/replacement_policies/fifo_rp.hh
b/src/mem/cache/replacement_policies/fifo_rp.hh
index 34067d5..77ff5d4 100644
--- a/src/mem/cache/replacement_policies/fifo_rp.hh
+++ b/src/mem/cache/replacement_policies/fifo_rp.hh
@@ -38,8 +38,10 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_FIFO_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_FIFO_RP_HH__

+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
-#include "params/FIFORP.hh"
+
+struct FIFORPParams;

class FIFORP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/lfu_rp.cc
b/src/mem/cache/replacement_policies/lfu_rp.cc
index ffa653e..299c74d 100644
--- a/src/mem/cache/replacement_policies/lfu_rp.cc
+++ b/src/mem/cache/replacement_policies/lfu_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/lfu_rp.hh"

+#include <cassert>
#include <memory>

+#include "params/LFURP.hh"
+
LFURP::LFURP(const Params *p)
: BaseReplacementPolicy(p)
{
diff --git a/src/mem/cache/replacement_policies/lfu_rp.hh
b/src/mem/cache/replacement_policies/lfu_rp.hh
index 8709e35..0c184c4 100644
--- a/src/mem/cache/replacement_policies/lfu_rp.hh
+++ b/src/mem/cache/replacement_policies/lfu_rp.hh
@@ -40,7 +40,8 @@
#define __MEM_CACHE_REPLACEMENT_POLICIES_LFU_RP_HH__

#include "mem/cache/replacement_policies/base.hh"
-#include "params/LFURP.hh"
+
+struct LFURPParams;

class LFURP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/lru_rp.cc
b/src/mem/cache/replacement_policies/lru_rp.cc
index 99e35db..9e7dcb5 100644
--- a/src/mem/cache/replacement_policies/lru_rp.cc
+++ b/src/mem/cache/replacement_policies/lru_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/lru_rp.hh"

+#include <cassert>
#include <memory>

+#include "params/LRURP.hh"
+
LRURP::LRURP(const Params *p)
: BaseReplacementPolicy(p)
{
diff --git a/src/mem/cache/replacement_policies/lru_rp.hh
b/src/mem/cache/replacement_policies/lru_rp.hh
index e8e708f..1b8a396 100644
--- a/src/mem/cache/replacement_policies/lru_rp.hh
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -39,7 +39,8 @@
#define __MEM_CACHE_REPLACEMENT_POLICIES_LRU_RP_HH__

#include "mem/cache/replacement_policies/base.hh"
-#include "params/LRURP.hh"
+
+struct LRURPParams;

class LRURP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/mru_rp.cc
b/src/mem/cache/replacement_policies/mru_rp.cc
index ff84fc3..b2e019f 100644
--- a/src/mem/cache/replacement_policies/mru_rp.cc
+++ b/src/mem/cache/replacement_policies/mru_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/mru_rp.hh"

+#include <cassert>
#include <memory>

+#include "params/MRURP.hh"
+
MRURP::MRURP(const Params *p)
: BaseReplacementPolicy(p)
{
diff --git a/src/mem/cache/replacement_policies/mru_rp.hh
b/src/mem/cache/replacement_policies/mru_rp.hh
index 11cc272..a95da04 100644
--- a/src/mem/cache/replacement_policies/mru_rp.hh
+++ b/src/mem/cache/replacement_policies/mru_rp.hh
@@ -38,8 +38,10 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_MRU_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_MRU_RP_HH__

+#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
-#include "params/MRURP.hh"
+
+struct MRURPParams;

class MRURP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/random_rp.cc
b/src/mem/cache/replacement_policies/random_rp.cc
index 6a0f353..c34d7ac 100644
--- a/src/mem/cache/replacement_policies/random_rp.cc
+++ b/src/mem/cache/replacement_policies/random_rp.cc
@@ -30,8 +30,11 @@

#include "mem/cache/replacement_policies/random_rp.hh"

+#include <cassert>
+#include <memory>
+
#include "base/random.hh"
-#include "mem/cache/blk.hh"
+#include "params/RandomRP.hh"

RandomRP::RandomRP(const Params *p)
: BaseReplacementPolicy(p)
diff --git a/src/mem/cache/replacement_policies/random_rp.hh
b/src/mem/cache/replacement_policies/random_rp.hh
index 5514961..bbceaab 100644
--- a/src/mem/cache/replacement_policies/random_rp.hh
+++ b/src/mem/cache/replacement_policies/random_rp.hh
@@ -38,7 +38,8 @@
#define __MEM_CACHE_REPLACEMENT_POLICIES_RANDOM_RP_HH__

#include "mem/cache/replacement_policies/base.hh"
-#include "params/RandomRP.hh"
+
+struct RandomRPParams;

class RandomRP : public BaseReplacementPolicy
{
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.cc
b/src/mem/cache/replacement_policies/second_chance_rp.cc
index 2560a98..64e667f 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.cc
+++ b/src/mem/cache/replacement_policies/second_chance_rp.cc
@@ -30,6 +30,10 @@

#include "mem/cache/replacement_policies/second_chance_rp.hh"

+#include <cassert>
+
+#include "params/SecondChanceRP.hh"
+
SecondChanceRP::SecondChanceRP(const Params *p)
: FIFORP(p)
{
diff --git a/src/mem/cache/replacement_policies/second_chance_rp.hh
b/src/mem/cache/replacement_policies/second_chance_rp.hh
index 5522d5e..84970e4 100644
--- a/src/mem/cache/replacement_policies/second_chance_rp.hh
+++ b/src/mem/cache/replacement_policies/second_chance_rp.hh
@@ -40,8 +40,10 @@
#ifndef __MEM_CACHE_REPLACEMENT_POLICIES_SECOND_CHANCE_RP_HH__
#define __MEM_CACHE_REPLACEMENT_POLICIES_SECOND_CHANCE_RP_HH__

+#include "mem/cache/replacement_policies/base.hh"
#include "mem/cache/replacement_policies/fifo_rp.hh"
-#include "params/SecondChanceRP.hh"
+
+struct SecondChanceRPParams;

class SecondChanceRP : public FIFORP
{
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 7d0a939..c7ea17b 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -48,8 +48,15 @@

#include "mem/cache/tags/base.hh"

+#include <cassert>
+
+#include "base/types.hh"
#include "mem/cache/base.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "sim/core.hh"
#include "sim/sim_exit.hh"
+#include "sim/system.hh"

BaseTags::BaseTags(const Params *p)
: ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1),
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 47bab43..806f63a 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -49,12 +49,15 @@
#ifndef __MEM_CACHE_TAGS_BASE_HH__
#define __MEM_CACHE_TAGS_BASE_HH__

+#include <cassert>
#include <string>

#include "base/callback.hh"
+#include "base/logging.hh"
#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/blk.hh"
-#include "mem/cache/replacement_policies/base.hh"
+#include "mem/packet.hh"
#include "params/BaseTags.hh"
#include "sim/clocked_object.hh"

diff --git a/src/mem/cache/tags/base_set_assoc.cc
b/src/mem/cache/tags/base_set_assoc.cc
index 5888d1f..d3420b4 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -47,9 +47,11 @@

#include "mem/cache/tags/base_set_assoc.hh"

+#include <cassert>
#include <string>

#include "base/intmath.hh"
+#include "mem/request.hh"

BaseSetAssoc::BaseSetAssoc(const Params *p)
:BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index 5a3e832..bf227c0 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -48,10 +48,11 @@
#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__

-#include <cassert>
-#include <cstring>
+#include <string>
#include <vector>

+#include "base/logging.hh"
+#include "base/types.hh"
#include "debug/CacheRepl.hh"
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
diff --git a/src/mem/cache/tags/cacheset.hh b/src/mem/cache/tags/cacheset.hh
index 5a34456..2675d45 100644
--- a/src/mem/cache/tags/cacheset.hh
+++ b/src/mem/cache/tags/cacheset.hh
@@ -49,6 +49,9 @@
#define __MEM_CACHE_TAGS_CACHESET_HH__

#include <cassert>
+#include <vector>
+
+#include "base/types.hh"

/**
* An associative set of cache blocks.
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 6abae2b..29dab3b 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -53,6 +53,7 @@

#include "base/intmath.hh"
#include "base/logging.hh"
+#include "mem/cache/base.hh"

FALRU::FALRU(const Params *p)
: BaseTags(p),
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index bec98e3..98a6457 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -49,11 +49,15 @@
#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
#define __MEM_CACHE_TAGS_FA_LRU_HH__

-#include <list>
+#include <cstdint>
+#include <string>
#include <unordered_map>

+#include "base/bitfield.hh"
#include "base/intmath.hh"
-#include "mem/cache/base.hh"
+#include "base/logging.hh"
+#include "base/statistics.hh"
+#include "base/types.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/tags/base.hh"
#include "mem/packet.hh"
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index 13e0fc5..11a2620 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -48,6 +48,10 @@

#include "mem/cache/write_queue.hh"

+#include <cassert>
+
+#include "mem/cache/write_queue_entry.hh"
+
WriteQueue::WriteQueue(const std::string &_label,
int num_entries, int reserve)
: Queue<WriteQueueEntry>(_label, num_entries, reserve)
diff --git a/src/mem/cache/write_queue.hh b/src/mem/cache/write_queue.hh
index 006d705..d9ace0d 100644
--- a/src/mem/cache/write_queue.hh
+++ b/src/mem/cache/write_queue.hh
@@ -45,10 +45,12 @@
#ifndef __MEM_CACHE_WRITE_QUEUE_HH__
#define __MEM_CACHE_WRITE_QUEUE_HH__

-#include <vector>
+#include <string>

+#include "base/types.hh"
#include "mem/cache/queue.hh"
#include "mem/cache/write_queue_entry.hh"
+#include "mem/packet.hh"

/**
* A write queue for all eviction packets, i.e. writebacks and clean
diff --git a/src/mem/cache/write_queue_entry.cc
b/src/mem/cache/write_queue_entry.cc
index 4aa174b..e393731 100644
--- a/src/mem/cache/write_queue_entry.cc
+++ b/src/mem/cache/write_queue_entry.cc
@@ -50,16 +50,13 @@

#include "mem/cache/write_queue_entry.hh"

-#include <algorithm>
#include <cassert>
#include <string>
-#include <vector>

#include "base/logging.hh"
#include "base/types.hh"
-#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
-#include "sim/core.hh"
+#include "mem/cache/base.hh"
+#include "mem/request.hh"

inline void
WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
diff --git a/src/mem/cache/write_queue_entry.hh
b/src/mem/cache/write_queue_entry.hh
index 40079b4..5a4b5a8 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -49,10 +49,16 @@
#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__

+#include <cassert>
+#include <iosfwd>
#include <list>
+#include <string>

#include "base/printable.hh"
+#include "base/types.hh"
#include "mem/cache/queue_entry.hh"
+#include "mem/packet.hh"
+#include "sim/core.hh"

class BaseCache;
--
To view, visit https://gem5-review.googlesource.com/10433
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Gerrit-Change-Number: 10433
Gerrit-PatchSet: 8
Gerrit-Owner: Nikos Nikoleris <***@arm.com>
Gerrit-Reviewer: Daniel Carvalho <***@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <***@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <***@arm.com>
Gerrit-MessageType: merged
Continue reading on narkive:
Loading...