Discussion:
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix recvTimingReq doWritebacks tick
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Daniel Carvalho (Gerrit)
2018-11-29 15:53:30 UTC
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Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14736


Change subject: mem-cache: Fix recvTimingReq doWritebacks tick
......................................................................

mem-cache: Fix recvTimingReq doWritebacks tick

Before being sent to the writebuffer, the evicted blocks
must be selected for replacement, and therefore the
access latency must be applied. The forward latency is
then applied on top of that delay.

Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc
Signed-off-by: Daniel R. Carvalho <***@yahoo.com.br>
---
M src/mem/cache/base.cc
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 641f1f5..94ff5c0 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -353,9 +353,10 @@
// access() will set the lat value.
satisfied = access(pkt, blk, lat, writebacks);

- // copy writebacks to write buffer here to ensure they logically
- // precede anything happening below
- doWritebacks(writebacks, forward_time);
+ // After the evicted blocks are selected, they must be forwarded
+ // to the write buffer to ensure they logically precede anything
+ // happening below
+ doWritebacks(writebacks, clockEdge(lat + forwardLatency));
}

// Here we charge the headerDelay that takes into account the latencies
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc
Gerrit-Change-Number: 14736
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <***@yahoo.com.br>
Gerrit-MessageType: newchange
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