Discussion:
[gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I
(too old to reply)
Alec Roelke
2016-09-14 22:45:02 UTC
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http://reviews.gem5.org/r/3624/
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Review request for Default.


Repository: gem5


Description
-------

Changeset 11620:80e562ddf946
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.


Diffs
-----

src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
a.out 8bc53d5565ba
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Jason Lowe-Power
2016-09-15 14:50:56 UTC
Permalink
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
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Thanks for the contribution. It looks pretty good! Could you give us a preview as to the other 4 patches? What is missing in this one?

I know nothing of how the ISA stuff works in gem5, but I reviewed most of the other parts of this patch.

Some high-level notes:

a.out probably shouldn't be in the patch.

Make sure you've updated all of the copyright information.

Have you run any of the RISC-V test suite on your code? (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably incorporate some (all?) of that into the regression tests. How much we include depends on how long the tests take.


ext/libelf/elf_common.h (line 176)
<http://reviews.gem5.org/r/3624/#comment7539>

It would be nice if this were aligned with the above.



src/arch/riscv/RiscvISA.py (line 51)
<http://reviews.gem5.org/r/3624/#comment7542>

I didn't see num_threads or num_vpes ever used. If these aren't used they should be removed.

Also, is `system` ever used?



src/arch/riscv/RiscvSystem.py (line 40)
<http://reviews.gem5.org/r/3624/#comment7545>

For all of these parameters: are they used by the RiscvSystem code? Will they be used in the future?

It looks like you copied a lot of this code from MIPS. If the code isn't applicable to RISC-V, it should be removed.



src/arch/riscv/RiscvSystem.py (line 46)
<http://reviews.gem5.org/r/3624/#comment7544>

Does this mean RISC-V only supports 32 bit? (I noticed the x86 mask is 64-bit.)



src/arch/riscv/RiscvSystem.py (line 54)
<http://reviews.gem5.org/r/3624/#comment7543>

Is this paraemter ever used? I didn't see it.


- Jason Lowe-Power
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 14, 2016, 10:45 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:80e562ddf946
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
a.out 8bc53d5565ba
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-15 18:18:16 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Thanks for the contribution. It looks pretty good! Could you give us a preview as to the other 4 patches? What is missing in this one?
I know nothing of how the ISA stuff works in gem5, but I reviewed most of the other parts of this patch.
a.out probably shouldn't be in the patch.
Make sure you've updated all of the copyright information.
Have you run any of the RISC-V test suite on your code? (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably incorporate some (all?) of that into the regression tests. How much we include depends on how long the tests take.
Yeah, I just noticed a.out. Is there a way to prevent SCons from producing it?

Which copyright information are you referring to? I went through and added it where I thought it was necessary, but I'm not very familiar with copyrights and licensing so I could have gotten it wrong.

I have tried running the some of the RISC-V tests, but they don't seem have the structure that GEM5 expects--for example, the entry point of rv64ui-p-add as defined by the ELF file doesn't exist in the disassembly.
Post by Alec Roelke
Post by Jason Lowe-Power
ext/libelf/elf_common.h, line 176
<http://reviews.gem5.org/r/3624/diff/1/?file=57831#file57831line176>
It would be nice if this were aligned with the above.
Do you mean the two lines immediately preceding it? It is aligned with most of the other EM definitions.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 3:19 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:849620cf01a3
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-09-15 18:39:09 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Thanks for the contribution. It looks pretty good! Could you give us a preview as to the other 4 patches? What is missing in this one?
I know nothing of how the ISA stuff works in gem5, but I reviewed most of the other parts of this patch.
a.out probably shouldn't be in the patch.
Make sure you've updated all of the copyright information.
Have you run any of the RISC-V test suite on your code? (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably incorporate some (all?) of that into the regression tests. How much we include depends on how long the tests take.
Yeah, I just noticed a.out. Is there a way to prevent SCons from producing it?
Which copyright information are you referring to? I went through and added it where I thought it was necessary, but I'm not very familiar with copyrights and licensing so I could have gotten it wrong.
I have tried running the some of the RISC-V tests, but they don't seem have the structure that GEM5 expects--for example, the entry point of rv64ui-p-add as defined by the ELF file doesn't exist in the disassembly.
I don't know how to get rid of a.out. If you find out, let me know too!

For the copyright. It seemed there were a number of files that you created that had other people's name on them (e.g., src/arch/riscv/RiscvInterrupts.py). Sincd you changed pretty much every line in that file, and created the file, you can add your copyright and author name.

Finally, that's unfortunate about the RISC-V tests. Is there a way to slightly modify the loading of gem5 to support them? Maybe this is something for a separate patch. It would be really great to run tests like this.


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 3:19 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:849620cf01a3
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-09-15 18:41:20 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
ext/libelf/elf_common.h, line 176
<http://reviews.gem5.org/r/3624/diff/1/?file=57831#file57831line176>
It would be nice if this were aligned with the above.
Do you mean the two lines immediately preceding it? It is aligned with most of the other EM definitions.
It's a silly nit, not very important. But the 243 doesn't appear to be in line with the 183. Same for the comment with the comment on the preceeding line. Maybe it's an accidental tab instead of spaces?


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 3:19 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:849620cf01a3
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-15 20:19:56 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Thanks for the contribution. It looks pretty good! Could you give us a preview as to the other 4 patches? What is missing in this one?
I know nothing of how the ISA stuff works in gem5, but I reviewed most of the other parts of this patch.
a.out probably shouldn't be in the patch.
Make sure you've updated all of the copyright information.
Have you run any of the RISC-V test suite on your code? (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably incorporate some (all?) of that into the regression tests. How much we include depends on how long the tests take.
Yeah, I just noticed a.out. Is there a way to prevent SCons from producing it?
Which copyright information are you referring to? I went through and added it where I thought it was necessary, but I'm not very familiar with copyrights and licensing so I could have gotten it wrong.
I have tried running the some of the RISC-V tests, but they don't seem have the structure that GEM5 expects--for example, the entry point of rv64ui-p-add as defined by the ELF file doesn't exist in the disassembly.
I don't know how to get rid of a.out. If you find out, let me know too!
For the copyright. It seemed there were a number of files that you created that had other people's name on them (e.g., src/arch/riscv/RiscvInterrupts.py). Sincd you changed pretty much every line in that file, and created the file, you can add your copyright and author name.
Finally, that's unfortunate about the RISC-V tests. Is there a way to slightly modify the loading of gem5 to support them? Maybe this is something for a separate patch. It would be really great to run tests like this.
The files that I didn't put my name in were not created by me; this project originated from earlier work we found on GitHub (basically from searching Google to see if someone had already done it). While there are heavy modifications that I made in general as beforehand very little was implemented, the files that I didn't touch at all, or that I only changed formatting for, I left with the original copyright information. Same for files I copied from MIPS without editing (I think that's only the TLB though).

The RISC-V GNU toolchain comes with an architecture simulator that is basically a dressed-down version of gem5's atomic CPU model and is able to run those tests, so it could be possible to modify gem5's ELF loader to work. On the other hand, if you want to run code compiled with the GNU toolchain on their simulator, you have to also use their proxy kernel, which crashes when you try to give it a RISC-V ISA test to run. I think the simulator probably uses a different entry point than the ELF file defines and the proxy kernel is responsible for reading it to determine the proper entry point, which gem5 does internally. Not to mention that the tests don't actually have any output themselves--whatever hardware or software is performing them is responsible for knowing if they've passed or not.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 3:19 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:849620cf01a3
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Diffs
-----
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-09-15 20:28:03 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Thanks for the contribution. It looks pretty good! Could you give us a preview as to the other 4 patches? What is missing in this one?
I know nothing of how the ISA stuff works in gem5, but I reviewed most of the other parts of this patch.
a.out probably shouldn't be in the patch.
Make sure you've updated all of the copyright information.
Have you run any of the RISC-V test suite on your code? (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably incorporate some (all?) of that into the regression tests. How much we include depends on how long the tests take.
Yeah, I just noticed a.out. Is there a way to prevent SCons from producing it?
Which copyright information are you referring to? I went through and added it where I thought it was necessary, but I'm not very familiar with copyrights and licensing so I could have gotten it wrong.
I have tried running the some of the RISC-V tests, but they don't seem have the structure that GEM5 expects--for example, the entry point of rv64ui-p-add as defined by the ELF file doesn't exist in the disassembly.
I don't know how to get rid of a.out. If you find out, let me know too!
For the copyright. It seemed there were a number of files that you created that had other people's name on them (e.g., src/arch/riscv/RiscvInterrupts.py). Sincd you changed pretty much every line in that file, and created the file, you can add your copyright and author name.
Finally, that's unfortunate about the RISC-V tests. Is there a way to slightly modify the loading of gem5 to support them? Maybe this is something for a separate patch. It would be really great to run tests like this.
The files that I didn't put my name in were not created by me; this project originated from earlier work we found on GitHub (basically from searching Google to see if someone had already done it). While there are heavy modifications that I made in general as beforehand very little was implemented, the files that I didn't touch at all, or that I only changed formatting for, I left with the original copyright information. Same for files I copied from MIPS without editing (I think that's only the TLB though).
The RISC-V GNU toolchain comes with an architecture simulator that is basically a dressed-down version of gem5's atomic CPU model and is able to run those tests, so it could be possible to modify gem5's ELF loader to work. On the other hand, if you want to run code compiled with the GNU toolchain on their simulator, you have to also use their proxy kernel, which crashes when you try to give it a RISC-V ISA test to run. I think the simulator probably uses a different entry point than the ELF file defines and the proxy kernel is responsible for reading it to determine the proper entry point, which gem5 does internally. Not to mention that the tests don't actually have any output themselves--whatever hardware or software is performing them is responsible for knowing if they've passed or not.
Ah, that makes sense with the copyright. Thanks for clarifying.

Too bad it wasn't easy to use their tests! Thanks for the info, though.


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8722
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 8:21 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:01bf9539be09
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-15 15:19:38 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Sept. 15, 2016, 3:19 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11620:849620cf01a3
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.


Diffs (updated)
-----

src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/linux/system.hh PRE-CREATION
src/arch/riscv/linux/system.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Alec Roelke
2016-09-15 20:21:20 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Sept. 15, 2016, 8:21 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11620:01bf9539be09
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Andreas Hansson
2016-09-15 20:26:00 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
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src/arch/riscv/RiscvISA.py (line 3)
<http://reviews.gem5.org/r/3624/#comment7548>

Regarding the license edits, the "normal" 3-clause BSD is the bottom two paragraphs.

I would encourage you to add your Copyright notice only for those paragraphs, and not the first one in the files with three. The top paragraph in this and other files with three paragraphs is an ARM addition that is technically an extension to the 3-clause BSD. You have a number of examples throughout the codebase.

Makes sense?


- Andreas Hansson
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 8:21 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:01bf9539be09
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-16 16:38:08 UTC
Permalink
Post by Alec Roelke
src/arch/riscv/RiscvISA.py, line 3
<http://reviews.gem5.org/r/3624/diff/2-3/?file=57895#file57895line3>
Regarding the license edits, the "normal" 3-clause BSD is the bottom two paragraphs.
I would encourage you to add your Copyright notice only for those paragraphs, and not the first one in the files with three. The top paragraph in this and other files with three paragraphs is an ARM addition that is technically an extension to the 3-clause BSD. You have a number of examples throughout the codebase.
Makes sense?
That does make sense. Thanks for your help.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8728
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 15, 2016, 8:53 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:cceb2cc47bdd
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-15 20:53:26 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Sept. 15, 2016, 8:53 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11620:cceb2cc47bdd
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Alec Roelke
2016-09-16 16:49:25 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Sept. 16, 2016, 4:49 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11620:3da42ffa5b4b
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Andreas Hansson
2016-09-27 20:53:25 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8737
-----------------------------------------------------------


Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights.

Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures?


ext/libelf/elf_common.h (line 175)
<http://reviews.gem5.org/r/3624/#comment7554>

Would be good to stick to the same spacing, and not change the AARCH64 line



src/arch/riscv/faults.hh (line 139)
<http://reviews.gem5.org/r/3624/#comment7555>

Could you perhaps elaborate on why this is ok as is?



src/arch/riscv/faults.cc (line 62)
<http://reviews.gem5.org/r/3624/#comment7556>

odd indentation here



src/arch/riscv/faults.cc (line 70)
<http://reviews.gem5.org/r/3624/#comment7557>

odd indentation



src/arch/riscv/idle_event.hh (line 47)
<http://reviews.gem5.org/r/3624/#comment7558>

Not that it matters, but could you update this as well?



src/arch/riscv/isa/base.isa (line 3)
<http://reviews.gem5.org/r/3624/#comment7566>

? Is that a legal entity?



src/arch/riscv/isa/bitfields.isa (line 3)
<http://reviews.gem5.org/r/3624/#comment7567>

Same as above



src/arch/riscv/mmapped_ipr.hh (line 43)
<http://reviews.gem5.org/r/3624/#comment7559>

RISCV has mmapped IPRs?



src/arch/riscv/pagetable.hh (line 81)
<http://reviews.gem5.org/r/3624/#comment7560>

What are the implications?

Also, should this class not inherint from Serializable?



src/arch/riscv/process.hh (line 32)
<http://reviews.gem5.org/r/3624/#comment7561>

ARCH_RISCV_...



src/arch/riscv/process.cc (line 116)
<http://reviews.gem5.org/r/3624/#comment7562>

This block has some formatting issues. Space around operators, and I think it is officially a convention to also keep the operator on the line of the first operand.



src/arch/riscv/tlb.cc (line 3)
<http://reviews.gem5.org/r/3624/#comment7565>

I am really surprise that this and a few other files do not have a Uni Virginia copyright. Is that intentional?



src/arch/riscv/tlb.cc (line 58)
<http://reviews.gem5.org/r/3624/#comment7563>

Not convention



src/arch/riscv/tlb.cc (line 89)
<http://reviews.gem5.org/r/3624/#comment7564>

?


- Andreas Hansson
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 16, 2016, 4:49 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:3da42ffa5b4b
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-28 01:36:26 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights.
Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures?
I didn't; I used cp and then hg add. Does hg copy do anything different?
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/faults.hh, line 139
<http://reviews.gem5.org/r/3624/diff/5/?file=58091#file58091line139>
Could you perhaps elaborate on why this is ok as is?
Currently this only supports SE mode, which doesn't have elevated privilege (which is also why the eret instruction is not implemented). That is a reminder to me of how I intended for that fault to change when elevated privilege is implemented (or a hint to the person who does it if I don't). Is it not appropriate to include it?
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/isa/base.isa, line 3
<http://reviews.gem5.org/r/3624/diff/5/?file=58099#file58099line3>
? Is that a legal entity?
Some of the files in this project were originally from a GitHub project by Austin Harris. In those cases, I left whatever copyright was originally there in addition to adding mine if I felt it was appropriate.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/tlb.cc, line 3
<http://reviews.gem5.org/r/3624/diff/5/?file=58133#file58133line3>
I am really surprise that this and a few other files do not have a Uni Virginia copyright. Is that intentional?
Files that I copied from other ISAs, and only made minor changes like names, I didn't feel merited that addition, so I left them as they are.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/pagetable.hh, line 81
<http://reviews.gem5.org/r/3624/diff/5/?file=58119#file58119line81>
What are the implications?
Also, should this class not inherint from Serializable?
This is copied from MIPS, with some name changes. I had been focused on getting RISC-V running, and haven't gotten to properly implementing the TLB yet.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/mmapped_ipr.hh, line 43
<http://reviews.gem5.org/r/3624/diff/5/?file=58118#file58118line43>
RISCV has mmapped IPRs?
This file was from the original GitHub project, and appears to be required by the CPU models.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/tlb.cc, line 58
<http://reviews.gem5.org/r/3624/diff/5/?file=58133#file58133line58>
Not convention
See my comment for pagetable.hh.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8737
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 16, 2016, 4:49 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:3da42ffa5b4b
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Andreas Hansson
2016-09-28 20:37:54 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights.
Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures?
I didn't; I used cp and then hg add. Does hg copy do anything different?
Yeah that is a bit of an issue. If you didn't actually use hg copy then all history of the file is lost. Sorry to be a drag, but could you redo it using hg copy?
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/faults.hh, line 139
<http://reviews.gem5.org/r/3624/diff/5/?file=58091#file58091line139>
Could you perhaps elaborate on why this is ok as is?
Currently this only supports SE mode, which doesn't have elevated privilege (which is also why the eret instruction is not implemented). That is a reminder to me of how I intended for that fault to change when elevated privilege is implemented (or a hint to the person who does it if I don't). Is it not appropriate to include it?
Fair enough. Feel free to leave it. I would imagine if you called out every location there would be tons of TODOs though :-)
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/isa/base.isa, line 3
<http://reviews.gem5.org/r/3624/diff/5/?file=58099#file58099line3>
? Is that a legal entity?
Some of the files in this project were originally from a GitHub project by Austin Harris. In those cases, I left whatever copyright was originally there in addition to adding mine if I felt it was appropriate.
I don't want to cause too much effort on your end, but I really think we need to get this right. Should Austin have used that entity for the copyright? Is it even a real legal entity? Could you reach out to him and check? We really need to get this right imho.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/mmapped_ipr.hh, line 43
<http://reviews.gem5.org/r/3624/diff/5/?file=58118#file58118line43>
RISCV has mmapped IPRs?
This file was from the original GitHub project, and appears to be required by the CPU models.
I see. Someone more familiar with the CPU model could perhaps comment? I find it odd that we need it when only ALPHA has the construct.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/tlb.cc, line 3
<http://reviews.gem5.org/r/3624/diff/5/?file=58133#file58133line3>
I am really surprise that this and a few other files do not have a Uni Virginia copyright. Is that intentional?
Files that I copied from other ISAs, and only made minor changes like names, I didn't feel merited that addition, so I left them as they are.
Makes sense. My rule is usually: If it's trivial to make the change using a sed script then don't bother.

As mentioned above, please make sure you use hg copy so that the revision history is maintained.


- Andreas


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8737
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 16, 2016, 4:49 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:3da42ffa5b4b
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-29 02:48:46 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights.
Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures?
I didn't; I used cp and then hg add. Does hg copy do anything different?
Yeah that is a bit of an issue. If you didn't actually use hg copy then all history of the file is lost. Sorry to be a drag, but could you redo it using hg copy?
Yes, I will go through and replace copies (or near copies) with hg copy.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/isa/base.isa, line 3
<http://reviews.gem5.org/r/3624/diff/5/?file=58099#file58099line3>
? Is that a legal entity?
Some of the files in this project were originally from a GitHub project by Austin Harris. In those cases, I left whatever copyright was originally there in addition to adding mine if I felt it was appropriate.
I don't want to cause too much effort on your end, but I really think we need to get this right. Should Austin have used that entity for the copyright? Is it even a real legal entity? Could you reach out to him and check? We really need to get this right imho.
I did some looking around the RISC-V website, and I believe the entity is "RISC-V Foundation" according to its copyright. I'll make the change, and add it to other files I think are related to the ISA specification like faults and registers.hh.
Post by Alec Roelke
Post by Andreas Hansson
src/arch/riscv/mmapped_ipr.hh, line 43
<http://reviews.gem5.org/r/3624/diff/5/?file=58118#file58118line43>
RISCV has mmapped IPRs?
This file was from the original GitHub project, and appears to be required by the CPU models.
I see. Someone more familiar with the CPU model could perhaps comment? I find it odd that we need it when only ALPHA has the construct.
I'll take a look at other non-Alpha ISAs and see if I can remove it.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8737
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 16, 2016, 4:49 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11620:3da42ffa5b4b
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 8bc53d5565ba
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 8bc53d5565ba
src/base/loader/object_file.hh 8bc53d5565ba
src/cpu/BaseCPU.py 8bc53d5565ba
src/sim/process.cc 8bc53d5565ba
tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-29 19:04:55 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Thanks again for getting this in shape. There are a few minor questions and comment on the patch, the most important one is related to the copyrights.
Also, I assume you have used hg copy for the files that are more or less 1:1 copies from other architectures?
I didn't; I used cp and then hg add. Does hg copy do anything different?
Yeah that is a bit of an issue. If you didn't actually use hg copy then all history of the file is lost. Sorry to be a drag, but could you redo it using hg copy?
Yes, I will go through and replace copies (or near copies) with hg copy.
I ended up only doing this for files that I copied myself (tlb, pagetable, and files in linux). I did not do this with files that could have been copies but were from the original GitHub project, as I don't know how they were created. If you think I should do this for them as well (and thus removing the copyrights from the GitHub project and replacing them with those of the equivalent files in MIPS), I can do it.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8737
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Sept. 29, 2016, 6:57 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:d0ecf8ecc940
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-09-29 18:57:48 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Sept. 29, 2016, 6:57 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11655:d0ecf8ecc940
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Alec Roelke
2016-10-10 16:59:40 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Oct. 10, 2016, 4:59 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11655:d4aaaa876749
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Alec Roelke
2016-10-11 17:17:47 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Oct. 11, 2016, 5:17 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11655:01b1d852e62e
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Andreas Hansson
2016-10-12 08:31:50 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8821
-----------------------------------------------------------



ext/libelf/elf_common.h (line 175)
<http://reviews.gem5.org/r/3624/#comment7606>

I think this particular line should not be changed and the line below should stick with the same spacing.



src/arch/riscv/isa_traits.hh (line 2)
<http://reviews.gem5.org/r/3624/#comment7607>

Was the spacing like this already?



src/arch/riscv/microcode_rom.hh (line 2)
<http://reviews.gem5.org/r/3624/#comment7608>

Was the spacing like this (in this and other files)? I think traditionally we did not align the legal entity names.



src/arch/riscv/process.cc (line 52)
<http://reviews.gem5.org/r/3624/#comment7609>

Is this based on a spec? If so, could you provide a pointer?



src/arch/riscv/process.cc (line 189)
<http://reviews.gem5.org/r/3624/#comment7610>

Not that it really matters, but feel free to use "auto"



src/arch/riscv/registers.hh (line 2)
<http://reviews.gem5.org/r/3624/#comment7611>

Spacing as before


Some minor questions and cosmetic issues.

Could you please also confirm that the files that are copied (and then modified) started out as hg copy (as previously discussed).

Besides that I think this is looking really good. Thanks Alec!

Steve, can we retire Alpha now to make up for the additional build and test time? :-)

- Andreas Hansson
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 11, 2016, 5:17 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:01b1d852e62e
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-12 16:25:21 UTC
Permalink
Post by Alec Roelke
src/arch/riscv/process.cc, line 189
<http://reviews.gem5.org/r/3624/diff/8/?file=59265#file59265line189>
Not that it really matters, but feel free to use "auto"
Actually I think I'll just use "int" as most people do. I'm not sure what I was thinking when I did this.
Post by Alec Roelke
src/arch/riscv/process.cc, line 52
<http://reviews.gem5.org/r/3624/diff/8/?file=59265#file59265line52>
Is this based on a spec? If so, could you provide a pointer?
I do remember referring to something when I was writing this, but it wasn't either of the volumes of the RISC-V specification and I can't find it anymore. I believe it was a source file somewhere in the riscv toolchain which had a comment describing the organization of program arguments upon entry. As for the values in the constructor of RiscvLiveProcess like stack_base, it didn't specify. I ended up using the ones from MIPS, except that the break point isn't rounded because that causes gem5 to crash when trying to run a program.
Post by Alec Roelke
ext/libelf/elf_common.h, line 175
<http://reviews.gem5.org/r/3624/diff/8/?file=59224#file59224line175>
I think this particular line should not be changed and the line below should stick with the same spacing.
That line is as it was before my patch. The other EM_X definitions all use a tab+spaces for alignment while EM_AARCH64 only uses spaces. I decided to align EM_RISCV with the others using a tab+spaces and leave EM_AARCH64 alone. Personally I think it should be changed so they all use only spaces, but I don't think this patch is the right place to do it.
Post by Alec Roelke
src/arch/riscv/microcode_rom.hh, line 2
<http://reviews.gem5.org/r/3624/diff/8/?file=59259#file59259line2>
Was the spacing like this (in this and other files)? I think traditionally we did not align the legal entity names.
It was (same for the others). I'll change it though.
Post by Alec Roelke
Some minor questions and cosmetic issues.
Could you please also confirm that the files that are copied (and then modified) started out as hg copy (as previously discussed).
Besides that I think this is looking really good. Thanks Alec!
Steve, can we retire Alpha now to make up for the additional build and test time? :-)
I went through and made sure to use hg copy on files that I copied. Ones that were similar but were from the original GitHub I didn't do this with, such as mmapped_ipr.hh (which I've learned is present in the other ISAs). Is there a way to check to make sure I did it right?

Also, as a heads up, I'm adding a sixth patch in the next few days that will have a (more) proper implementation of the files in the linux/ directory. Currently the system calls technically work, but the structure of the data structures for calls like stat aren't what RISC-V programs are expecting. So far I've only run into this for stat and fstat.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8821
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 11, 2016, 5:17 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:01b1d852e62e
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Andreas Hansson
2016-10-13 13:24:08 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Some minor questions and cosmetic issues.
Could you please also confirm that the files that are copied (and then modified) started out as hg copy (as previously discussed).
Besides that I think this is looking really good. Thanks Alec!
Steve, can we retire Alpha now to make up for the additional build and test time? :-)
I went through and made sure to use hg copy on files that I copied. Ones that were similar but were from the original GitHub I didn't do this with, such as mmapped_ipr.hh (which I've learned is present in the other ISAs). Is there a way to check to make sure I did it right?
Also, as a heads up, I'm adding a sixth patch in the next few days that will have a (more) proper implementation of the files in the linux/ directory. Currently the system calls technically work, but the structure of the data structures for calls like stat aren't what RISC-V programs are expecting. So far I've only run into this for stat and fstat.
All sounds good. I'm not aware of any good way to check besides manually inspecting the patch. If you have someone else's copyright and it says "new" then clearly something is not right.

Could you close (fixed or drop) the issues that are open?


- Andreas


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8821
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 12, 2016, 4:46 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:e462a5c2cca2
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
Signed-off by: Alec Roelke
Diffs
-----
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-13 16:46:14 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Some minor questions and cosmetic issues.
Could you please also confirm that the files that are copied (and then modified) started out as hg copy (as previously discussed).
Besides that I think this is looking really good. Thanks Alec!
Steve, can we retire Alpha now to make up for the additional build and test time? :-)
I went through and made sure to use hg copy on files that I copied. Ones that were similar but were from the original GitHub I didn't do this with, such as mmapped_ipr.hh (which I've learned is present in the other ISAs). Is there a way to check to make sure I did it right?
Also, as a heads up, I'm adding a sixth patch in the next few days that will have a (more) proper implementation of the files in the linux/ directory. Currently the system calls technically work, but the structure of the data structures for calls like stat aren't what RISC-V programs are expecting. So far I've only run into this for stat and fstat.
All sounds good. I'm not aware of any good way to check besides manually inspecting the patch. If you have someone else's copyright and it says "new" then clearly something is not right.
Could you close (fixed or drop) the issues that are open?
I went through and did hg copy on all the files that could have been copies (basically that didn't have my copyright on them). There are a couple of problem files, though: vtophys.hh, types.hh, remote_gdb.cc, and remote_gdb.hh. I did not create them, but they aren't copies of any of the other architectures since they're basically stubs (although in the RV64A patch I do modify types.hh and have my copyright added). Should I leave them as is?


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8821
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 12, 2016, 4:46 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:e462a5c2cca2
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
Signed-off by: Alec Roelke
Diffs
-----
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Andreas Hansson
2016-10-13 16:58:18 UTC
Permalink
Post by Alec Roelke
Post by Andreas Hansson
Some minor questions and cosmetic issues.
Could you please also confirm that the files that are copied (and then modified) started out as hg copy (as previously discussed).
Besides that I think this is looking really good. Thanks Alec!
Steve, can we retire Alpha now to make up for the additional build and test time? :-)
I went through and made sure to use hg copy on files that I copied. Ones that were similar but were from the original GitHub I didn't do this with, such as mmapped_ipr.hh (which I've learned is present in the other ISAs). Is there a way to check to make sure I did it right?
Also, as a heads up, I'm adding a sixth patch in the next few days that will have a (more) proper implementation of the files in the linux/ directory. Currently the system calls technically work, but the structure of the data structures for calls like stat aren't what RISC-V programs are expecting. So far I've only run into this for stat and fstat.
All sounds good. I'm not aware of any good way to check besides manually inspecting the patch. If you have someone else's copyright and it says "new" then clearly something is not right.
Could you close (fixed or drop) the issues that are open?
I went through and did hg copy on all the files that could have been copies (basically that didn't have my copyright on them). There are a couple of problem files, though: vtophys.hh, types.hh, remote_gdb.cc, and remote_gdb.hh. I did not create them, but they aren't copies of any of the other architectures since they're basically stubs (although in the RV64A patch I do modify types.hh and have my copyright added). Should I leave them as is?
No objections from my end.

Thanks again for all the effort in getting this right.


- Andreas


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8821
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-12 16:46:41 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Oct. 12, 2016, 4:46 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11655:e462a5c2cca2
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Alec Roelke
2016-10-13 16:48:09 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Oct. 13, 2016, 4:48 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Andreas Hansson
2016-10-13 17:01:15 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8836
-----------------------------------------------------------

Ship it!


Looks good to me. It would be good if someone else could review this as well.

- Andreas Hansson
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-10-20 14:35:10 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------


Sorry for the slow reviewing. I have a few minor changes.

First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.

Second, when I apply the patch and try to compile, I get a number of errors. Most are about the endianness functions:
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`

Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.

I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).

- Jason Lowe-Power
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-20 21:25:58 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.

I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-10-21 14:41:47 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.

I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-21 15:45:22 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).

I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 4:48 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-10-21 20:42:50 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.

I have another question, though...

I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.

When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```

What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.

Thanks for all your work!


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-21 21:18:59 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.
I have another question, though...
I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.
When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```
What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.
Thanks for all your work!
I have been using riscv64-unknown-elf-gcc rather than riscv64-unknown-gnu-linux-gcc. I don't know if riscv-gnu-toolchain will build riscv64-unknown-elf-gcc, but you can get riscv-tools and build that, and then you get riscv64-unknown-elf-gcc (and spike if you're interested in playing around with that). I tried using riscv64-unknown-gnu-linux-gcc, but I encountered a problem where gem5 would return from a function and then read 0x00000000 as an instruction even though the instruction at the corresponding PC in the assembly is valid.

This doesn't appear to be your problem, though. Your instruction appears to be a multiply instruction, which isn't part of RV64I. I'm not sure why the compiler would do that when you specified -march=RV64I unless that's just a suggestion and doesn't bind it to anything. However, I do recall that riscv64-unknown-elf-gcc should not use a multiply when invoking printf with only a single argument that's a string literal.

I think your options are to either apply patch 2, which adds integer multiply instructions, or try using riscv64-uknown-elf-gcc instead of riscv64-unknown-gnu-linux-gcc. I would recommend the former, since trying the latter might cause a different problem that I mentioned earlier. If all you want to do is run something, there should also be a precompiled hello binary in tests/test-progs/hello/bin/riscv/linux/.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-21 21:22:10 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.
I have another question, though...
I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.
When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```
What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.
Thanks for all your work!
I have been using riscv64-unknown-elf-gcc rather than riscv64-unknown-gnu-linux-gcc. I don't know if riscv-gnu-toolchain will build riscv64-unknown-elf-gcc, but you can get riscv-tools and build that, and then you get riscv64-unknown-elf-gcc (and spike if you're interested in playing around with that). I tried using riscv64-unknown-gnu-linux-gcc, but I encountered a problem where gem5 would return from a function and then read 0x00000000 as an instruction even though the instruction at the corresponding PC in the assembly is valid.
This doesn't appear to be your problem, though. Your instruction appears to be a multiply instruction, which isn't part of RV64I. I'm not sure why the compiler would do that when you specified -march=RV64I unless that's just a suggestion and doesn't bind it to anything. However, I do recall that riscv64-unknown-elf-gcc should not use a multiply when invoking printf with only a single argument that's a string literal.
I think your options are to either apply patch 2, which adds integer multiply instructions, or try using riscv64-uknown-elf-gcc instead of riscv64-unknown-gnu-linux-gcc. I would recommend the former, since trying the latter might cause a different problem that I mentioned earlier. If all you want to do is run something, there should also be a precompiled hello binary in tests/test-progs/hello/bin/riscv/linux/.
I forgot to mention, I've just been using straight configs/example/se.py to run my code. I don't think that should make a difference, though.


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-10-21 22:29:40 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.
I have another question, though...
I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.
When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```
What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.
Thanks for all your work!
I have been using riscv64-unknown-elf-gcc rather than riscv64-unknown-gnu-linux-gcc. I don't know if riscv-gnu-toolchain will build riscv64-unknown-elf-gcc, but you can get riscv-tools and build that, and then you get riscv64-unknown-elf-gcc (and spike if you're interested in playing around with that). I tried using riscv64-unknown-gnu-linux-gcc, but I encountered a problem where gem5 would return from a function and then read 0x00000000 as an instruction even though the instruction at the corresponding PC in the assembly is valid.
This doesn't appear to be your problem, though. Your instruction appears to be a multiply instruction, which isn't part of RV64I. I'm not sure why the compiler would do that when you specified -march=RV64I unless that's just a suggestion and doesn't bind it to anything. However, I do recall that riscv64-unknown-elf-gcc should not use a multiply when invoking printf with only a single argument that's a string literal.
I think your options are to either apply patch 2, which adds integer multiply instructions, or try using riscv64-uknown-elf-gcc instead of riscv64-unknown-gnu-linux-gcc. I would recommend the former, since trying the latter might cause a different problem that I mentioned earlier. If all you want to do is run something, there should also be a precompiled hello binary in tests/test-progs/hello/bin/riscv/linux/.
I forgot to mention, I've just been using straight configs/example/se.py to run my code. I don't think that should make a difference, though.
Ok. I'll play around with it soon.

The binary isn't in the diff, unfortunately. That's why I was compiling it on my own. If I still have issues I may ask you to send me the binary off-list.


- Jason


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-22 00:47:03 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.
I have another question, though...
I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.
When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```
What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.
Thanks for all your work!
I have been using riscv64-unknown-elf-gcc rather than riscv64-unknown-gnu-linux-gcc. I don't know if riscv-gnu-toolchain will build riscv64-unknown-elf-gcc, but you can get riscv-tools and build that, and then you get riscv64-unknown-elf-gcc (and spike if you're interested in playing around with that). I tried using riscv64-unknown-gnu-linux-gcc, but I encountered a problem where gem5 would return from a function and then read 0x00000000 as an instruction even though the instruction at the corresponding PC in the assembly is valid.
This doesn't appear to be your problem, though. Your instruction appears to be a multiply instruction, which isn't part of RV64I. I'm not sure why the compiler would do that when you specified -march=RV64I unless that's just a suggestion and doesn't bind it to anything. However, I do recall that riscv64-unknown-elf-gcc should not use a multiply when invoking printf with only a single argument that's a string literal.
I think your options are to either apply patch 2, which adds integer multiply instructions, or try using riscv64-uknown-elf-gcc instead of riscv64-unknown-gnu-linux-gcc. I would recommend the former, since trying the latter might cause a different problem that I mentioned earlier. If all you want to do is run something, there should also be a precompiled hello binary in tests/test-progs/hello/bin/riscv/linux/.
I forgot to mention, I've just been using straight configs/example/se.py to run my code. I don't think that should make a difference, though.
Ok. I'll play around with it soon.
The binary isn't in the diff, unfortunately. That's why I was compiling it on my own. If I still have issues I may ask you to send me the binary off-list.
Oh, I thought I had added it. Should I not add it?


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8945
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Jason Lowe-Power
2016-10-22 01:56:21 UTC
Permalink
Post by Alec Roelke
Post by Jason Lowe-Power
Sorry for the slow reviewing. I have a few minor changes.
First, when I apply the patch, I get a number of errors from the style checker. Make sure you're using the most up-to-date version of gem5 when you rebase your patch.
`build/RISCV/config/the_isa.hh:25:16: error: 'gtoh' is not a member of 'RiscvISA'`
Third, I'm getting a number of "unused-variable" warnings (errors). If the variables are used for debugging (e.g., in asserts) you can use the macro M5_VAR_USED after the variable name and before the assignment.
I'm not sure if the problem is that you've based this on an older version of gem5, or maybe we're just using different compilers (I'm use gcc-4.8).
I ignored a few of the style warnings because I saw some other places in gem5's code where the character limit was ignored. I'll go back through and try to fix them all though. I think for remote_gdb there are some (a lot of) warnings about "invalid control characters" that I wasn't sure how to fix.
I built this using a system running Ubuntu 16.04, which has gcc 5.3 and doesn't have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast.
Thanks for fixing the style errors. Although there are still some places that don't follow the style guide in the code, we try to fix all of these as we find them. Definitely any new code should follow all of the style guidelines.
I'm not sure why I was having errors yesterday. They've magically resolved themselves overnight. Hopefully you didn't spend too much time looking into it :).
Okay, I'll fix the rest of them, then (and in other patches too).
I actually figured it out. In my original code, there was a weird bug in isa/includes.isa where sim/system.hh had to be included out of order in, I believe, the decoder or the errors you mentioned would pop up. I added an include for it into registers.hh and it fixed it.
I see, I bet it was that I fixed some of the include orderings and got that error.
I have another question, though...
I'm trying to test this out myself. I downloaded the compiler from https://github.com/riscv/riscv-gnu-toolchain and then build hello with `riscv64-unknown-linux-gnu-gcc ../../../src/hello.c -o hello -static -march=RV64I`.
When trying to run the binary I'm getting the error
```
panic: Unknown instruction 0x03755433 at pc 0x000000000002e1b8
@ tick 318000
```
What am I doing wrong? I'm using configs/learning_gem5/part1/simple.py with changes to use the atomic CPU instead of the timing.
Thanks for all your work!
I have been using riscv64-unknown-elf-gcc rather than riscv64-unknown-gnu-linux-gcc. I don't know if riscv-gnu-toolchain will build riscv64-unknown-elf-gcc, but you can get riscv-tools and build that, and then you get riscv64-unknown-elf-gcc (and spike if you're interested in playing around with that). I tried using riscv64-unknown-gnu-linux-gcc, but I encountered a problem where gem5 would return from a function and then read 0x00000000 as an instruction even though the instruction at the corresponding PC in the assembly is valid.
This doesn't appear to be your problem, though. Your instruction appears to be a multiply instruction, which isn't part of RV64I. I'm not sure why the compiler would do that when you specified -march=RV64I unless that's just a suggestion and doesn't bind it to anything. However, I do recall that riscv64-unknown-elf-gcc should not use a multiply when invoking printf with only a single argument that's a string literal.
I think your options are to either apply patch 2, which adds integer multiply instructions, or try using riscv64-uknown-elf-gcc instead of riscv64-unknown-gnu-linux-gcc. I would recommend the former, since trying the latter might cause a different problem that I mentioned earlier. If all you want to do is run something, there should also be a precompiled hello binary in tests/test-progs/hello/bin/riscv/linux/.
I forgot to mention, I've just been using straight configs/example/se.py to run my code. I don't think that should make a difference, though.
Ok. I'll play around with it soon.
The binary isn't in the diff, unfortunately. That's why I was compiling it on my own. If I still have issues I may ask you to send me the binary off-list.
Oh, I thought I had added it. Should I not add it?
You added it. It just doesn't show up on reviewboard. It's a reviewboard issue.


- Jason


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-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Steve Reinhardt
2016-10-20 19:10:27 UTC
Permalink
-----------------------------------------------------------
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-----------------------------------------------------------


Looks good overall! Just a few minor nits, really.


ext/libelf/elf_common.h (line 176)
<http://reviews.gem5.org/r/3624/#comment7694>

misspelled 'Berkeley' :)



src/arch/riscv/isa/formats/mem.isa (line 51)
<http://reviews.gem5.org/r/3624/#comment7697>

space after 'if' (here and below)... even though these aren't C++ files, the C++ code should still follow the style guide



src/arch/riscv/isa_traits.hh (line 67)
<http://reviews.gem5.org/r/3624/#comment7692>

shouldn't this be 'false'? or is the comment incorrect?



src/arch/riscv/microcode_rom.hh (line 38)
<http://reviews.gem5.org/r/3624/#comment7693>

Do you really need a microcode ROM? Seems like this whole file should not be necessary.


- Steve Reinhardt
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 13, 2016, 9:48 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11655:fce68047f694
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h 49cbf4bb0d36
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc 49cbf4bb0d36
src/base/loader/object_file.hh 49cbf4bb0d36
src/cpu/BaseCPU.py 49cbf4bb0d36
src/sim/process.cc 49cbf4bb0d36
tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-21 18:12:30 UTC
Permalink
Post by Alec Roelke
src/arch/riscv/microcode_rom.hh, line 38
<http://reviews.gem5.org/r/3624/diff/10/?file=59931#file59931line38>
Do you really need a microcode ROM? Seems like this whole file should not be necessary.
I don't think it should be required, but microcode_rom.hh is required by mem/abstract_mem.cc and the type MicrocodeRom is needed by several files in cpu, so it's just copied from another ISA.


- Alec


-----------------------------------------------------------
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-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-10-21 18:12:03 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Oct. 21, 2016, 6:12 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Jason Lowe-Power
2016-10-27 16:37:52 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review8997
-----------------------------------------------------------

Ship it!


Sorry for the delay. I finally got everything working and it looks good to me! I'll start testing the other patches in the series soon.

- Jason Lowe-Power
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 6:12 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Tony Gutierrez
2016-10-31 23:33:30 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review9006
-----------------------------------------------------------


A few minor things, otherwise it looks pretty good.


src/arch/riscv/decoder.hh (line 109)
<http://reviews.gem5.org/r/3624/#comment7761>

nullptr. Fix throughout.



src/arch/riscv/faults.hh (line 51)
<http://reviews.gem5.org/r/3624/#comment7762>

Are these duplicate values right?



src/arch/riscv/faults.hh (line 129)
<http://reviews.gem5.org/r/3624/#comment7763>

Public/private should be indented 2 spaces. Fix throughout.


- Tony Gutierrez
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 21, 2016, 11:12 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:f84b3613acf4
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
Signed-off by: Alec Roelke
Diffs
-----
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/sim/process.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/arch/riscv/utility.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/cpu/BaseCPU.py b3d5f0e9e258
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-11-01 01:29:38 UTC
Permalink
Post by Alec Roelke
src/arch/riscv/faults.hh, line 51
<http://reviews.gem5.org/r/3624/diff/11/?file=61979#file61979line51>
Are these duplicate values right?
Yes. RISC-V doesn't distinguish between misaligned addresses with store instructions or AMO instructions, but since it does distinguish between those and misaligned load addresses, I felt having separate constants with the same value would be appropriate. The values can be found on page 35 of the "Draft Privileged ISA Specification v1.9" (https://riscv.org/specifications/privileged-isa/).


- Alec


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review9006
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Nov. 1, 2016, 1:29 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:ccda87b39fe5
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/cpu/BaseCPU.py b3d5f0e9e258
src/sim/process.cc b3d5f0e9e258
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Tony Gutierrez
2016-11-01 15:39:44 UTC
Permalink
Post by Alec Roelke
src/arch/riscv/faults.hh, line 51
<http://reviews.gem5.org/r/3624/diff/11/?file=61979#file61979line51>
Are these duplicate values right?
Yes. RISC-V doesn't distinguish between misaligned addresses with store instructions or AMO instructions, but since it does distinguish between those and misaligned load addresses, I felt having separate constants with the same value would be appropriate. The values can be found on page 35 of the "Draft Privileged ISA Specification v1.9" (https://riscv.org/specifications/privileged-isa/).
Thanks for the clarification, could you add a comment to the source to this effect?


- Tony


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review9006
-----------------------------------------------------------
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 31, 2016, 6:29 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:ccda87b39fe5
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/cpu/BaseCPU.py b3d5f0e9e258
src/sim/process.cc b3d5f0e9e258
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Alec Roelke
2016-11-01 01:29:21 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------

(Updated Nov. 1, 2016, 1:29 a.m.)


Review request for Default.


Repository: gem5


Description (updated)
-------

Changeset 11688:ccda87b39fe5
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke


Diffs (updated)
-----

build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/cpu/BaseCPU.py b3d5f0e9e258
src/sim/process.cc b3d5f0e9e258
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION

Diff: http://reviews.gem5.org/r/3624/diff/


Testing
-------


Thanks,

Alec Roelke
Tony Gutierrez
2016-11-01 15:39:47 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3624/#review9015
-----------------------------------------------------------

Ship it!


Ship It!

- Tony Gutierrez
Post by Alec Roelke
-----------------------------------------------------------
http://reviews.gem5.org/r/3624/
-----------------------------------------------------------
(Updated Oct. 31, 2016, 6:29 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 11688:ccda87b39fe5
---------------------------
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke
Diffs
-----
build_opts/RISCV PRE-CREATION
ext/libelf/elf_common.h b3d5f0e9e258
src/arch/riscv/RiscvISA.py PRE-CREATION
src/arch/riscv/RiscvInterrupts.py PRE-CREATION
src/arch/riscv/RiscvSystem.py PRE-CREATION
src/arch/riscv/RiscvTLB.py PRE-CREATION
src/arch/riscv/SConscript PRE-CREATION
src/arch/riscv/SConsopts PRE-CREATION
src/arch/riscv/decoder.hh PRE-CREATION
src/arch/riscv/decoder.cc PRE-CREATION
src/arch/riscv/faults.hh PRE-CREATION
src/arch/riscv/faults.cc PRE-CREATION
src/arch/riscv/idle_event.hh PRE-CREATION
src/arch/riscv/idle_event.cc PRE-CREATION
src/arch/riscv/interrupts.hh PRE-CREATION
src/arch/riscv/interrupts.cc PRE-CREATION
src/arch/riscv/isa.hh PRE-CREATION
src/arch/riscv/isa.cc PRE-CREATION
src/arch/riscv/isa/base.isa PRE-CREATION
src/arch/riscv/isa/bitfields.isa PRE-CREATION
src/arch/riscv/isa/decoder.isa PRE-CREATION
src/arch/riscv/isa/formats/basic.isa PRE-CREATION
src/arch/riscv/isa/formats/formats.isa PRE-CREATION
src/arch/riscv/isa/formats/mem.isa PRE-CREATION
src/arch/riscv/isa/formats/type.isa PRE-CREATION
src/arch/riscv/isa/formats/unknown.isa PRE-CREATION
src/arch/riscv/isa/includes.isa PRE-CREATION
src/arch/riscv/isa/main.isa PRE-CREATION
src/arch/riscv/isa/operands.isa PRE-CREATION
src/arch/riscv/isa_traits.hh PRE-CREATION
src/arch/riscv/kernel_stats.hh PRE-CREATION
src/arch/riscv/linux/linux.hh PRE-CREATION
src/arch/riscv/linux/linux.cc PRE-CREATION
src/arch/riscv/linux/process.hh PRE-CREATION
src/arch/riscv/vtophys.hh PRE-CREATION
src/base/loader/elf_object.cc b3d5f0e9e258
src/base/loader/object_file.hh b3d5f0e9e258
src/cpu/BaseCPU.py b3d5f0e9e258
src/sim/process.cc b3d5f0e9e258
src/arch/riscv/linux/process.cc PRE-CREATION
src/arch/riscv/locked_mem.hh PRE-CREATION
src/arch/riscv/microcode_rom.hh PRE-CREATION
src/arch/riscv/mmapped_ipr.hh PRE-CREATION
src/arch/riscv/pagetable.hh PRE-CREATION
src/arch/riscv/pagetable.cc PRE-CREATION
src/arch/riscv/pra_constants.hh PRE-CREATION
src/arch/riscv/process.hh PRE-CREATION
src/arch/riscv/process.cc PRE-CREATION
src/arch/riscv/pseudo_inst.hh PRE-CREATION
src/arch/riscv/registers.hh PRE-CREATION
src/arch/riscv/remote_gdb.hh PRE-CREATION
src/arch/riscv/remote_gdb.cc PRE-CREATION
src/arch/riscv/stacktrace.hh PRE-CREATION
src/arch/riscv/stacktrace.cc PRE-CREATION
src/arch/riscv/system.hh PRE-CREATION
src/arch/riscv/system.cc PRE-CREATION
src/arch/riscv/tlb.hh PRE-CREATION
src/arch/riscv/tlb.cc PRE-CREATION
src/arch/riscv/types.hh PRE-CREATION
src/arch/riscv/utility.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3624/diff/
Testing
-------
Thanks,
Alec Roelke
Loading...