Discussion:
[gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model
(too old to reply)
Ali Saidi via gem5-dev
2014-05-30 15:23:02 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------

Review request for Default.


Repository: gem5


Description
-------

Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036


Diffs
-----

build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/cpu/minor/Expr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/expr.hh PRE-CREATION
src/cpu/minor/expr.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION

Diff: http://reviews.gem5.org/r/2279/diff/


Testing
-------

Boots Linux and runs regression tests for ALPHA and ARM.


Thanks,

Ali Saidi
Steve Reinhardt via gem5-dev
2014-06-04 20:15:39 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5125
-----------------------------------------------------------


Nice! I didn't have time to read all the code closely, but I did notice a few things, and wanted to give feedback before I forgot.

Basically the comments boil down to three things:

1. There are several pieces (Named, TickedModule, maybe the Expr stuff) that look more broadly useful, and it would be nice not to bury them inside of the CPU model
2. The report() functionality, at least, looks similar to methods on other objects like dump() and print(); we might want to standardize on this
3. A few minor (no pun intended) places where there are formatting inconsistencies with undocumented gem5 conventions

As far as #3, I'd be glad to update the coding style page appropriately if people agree that the things I've called out below should be standardized.

Where does the name come from? Will you be committing a 'Major' model in the future?



src/cpu/minor/Expr.py
<http://reviews.gem5.org/r/2279/#comment4643>

This is pretty interesting... it would be nice to generalize this capability and not make it Minor-specific



src/cpu/minor/cpu.hh
<http://reviews.gem5.org/r/2279/#comment4634>

I don't know why, and I know it's not in the style guide, but all the gem5 code I've seen (or written) has the colon at the beginning of the second line, not the end of the first... might as well be consistent



src/cpu/minor/decode.cc
<http://reviews.gem5.org/r/2279/#comment4635>

another implicit, undocumented consistency thing: continued arg lists get indented to the opening paren, not just four spaces



src/cpu/minor/dyn_inst.hh
<http://reviews.gem5.org/r/2279/#comment4636>

I'd put a paren at the beginning of this expression, then indent so all the lines start one column past the paren... keeps the assignment '=' from blending in with all the '=='



src/cpu/minor/scoreboard.cc
<http://reviews.gem5.org/r/2279/#comment4637>

space after for



src/cpu/minor/scoreboard.cc
<http://reviews.gem5.org/r/2279/#comment4638>

opening brace at end of previous line (here & a few places below)



src/cpu/minor/ticked.hh
<http://reviews.gem5.org/r/2279/#comment4639>

This seems like it could be useful outside of Minor... perhaps we should put it in src/sim, or even just integrate this functionality with ClockedObject



src/cpu/minor/ticked.hh
<http://reviews.gem5.org/r/2279/#comment4640>

We also have various objects that have dump() or print() methods... it would be nice to standardize this



src/cpu/minor/ticked.hh
<http://reviews.gem5.org/r/2279/#comment4641>

integrating with ClockedObject would eliminate the multiple inheritance... not that MI is totally evil, but it's always better to avoid it when possible



src/cpu/minor/trace.hh
<http://reviews.gem5.org/r/2279/#comment4642>

This would be very useful outside of Minor... should go in src/base/trace.hh, IMO



src/cpu/static_inst.hh
<http://reviews.gem5.org/r/2279/#comment4633>

blank line here would be nice


- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated May 30, 2014, 8:23 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/cpu/minor/Expr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/expr.hh PRE-CREATION
src/cpu/minor/expr.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Andrew Bardsley via gem5-dev
2014-06-05 10:06:32 UTC
Permalink
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
Nice! I didn't have time to read all the code closely, but I did notice a few things, and wanted to give feedback before I forgot.
1. There are several pieces (Named, TickedModule, maybe the Expr stuff) that look more broadly useful, and it would be nice not to bury them inside of the CPU model
2. The report() functionality, at least, looks similar to methods on other objects like dump() and print(); we might want to standardize on this
3. A few minor (no pun intended) places where there are formatting inconsistencies with undocumented gem5 conventions
As far as #3, I'd be glad to update the coding style page appropriately if people agree that the things I've called out below should be standardized.
Where does the name come from? Will you be committing a 'Major' model in the future?
I'll make separate replies for each of your points but here's the philosophy:

1. I'll address these one by one as the arguments are a bit different for each
2. Report probably has too specific a name, I don't think it fits with the dump/print pattern as well as it may appear. I'll off more reasoning below
3. I'll fix/comment. I only have one personal strong style dislike to express (== plea to not standardise).

Oh, the name. M(odel|icroprocessor)INORder. The model has gone through a few names but that was the one that seemed to stick. Unfortunately it doesn't really pass the tell-apart-from-a-dictionary-word test and I find myself having to say 'Minor CPU' a bit too much, so it's not absolutely ideal.

There are no plans for a Major. Sorry to raise hopes ;)
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/Expr.py, line 48
<http://reviews.gem5.org/r/2279/diff/1/?file=39827#file39827line48>
This is pretty interesting... it would be nice to generalize this capability and not make it Minor-specific
Yeah. MinorExpr could easily be hoisted upwards and lose its Minor prefix (It doesn't have any dependencies on Minor).

Maybe TimingExpr or something like that (to disambiguate and suggest its function a bit more) would be a good name?
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/cpu.hh, line 88
<http://reviews.gem5.org/r/2279/diff/1/?file=39833#file39833line88>
I don't know why, and I know it's not in the style guide, but all the gem5 code I've seen (or written) has the colon at the beginning of the second line, not the end of the first... might as well be consistent
I've run a couple of regexps over the codebase (quick and dirty, not checked all the matches):

'^ * : [a-z]' (next line :) 257 lines
'\) :'$ (trailing :) 394 lines

If you drop uses in src/arch/... (as the archs seem to have slightly more fast and loose enforcement of the style rules):

next line: 231 lines
trailing: 125 lines

So next line seems to be winning.

I have no real preference.
Do you want to add this to the style guide?
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/decode.cc, line 153
<http://reviews.gem5.org/r/2279/diff/1/?file=39836#file39836line153>
another implicit, undocumented consistency thing: continued arg lists get indented to the opening paren, not just four spaces
Erm, yeah, I really strongly disagree with hanging arguments. I find they waste too much space (and break my indentation fascist person rule about always indenting exactly once and always the same size, but that's my psychological problem to deal with ;) ).

I throw myself of the mercy of the style enforcement court and plea for hanging arguments *not* become an explicit style rule.
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/dyn_inst.hh, line 126
<http://reviews.gem5.org/r/2279/diff/1/?file=39837#file39837line126>
I'd put a paren at the beginning of this expression, then indent so all the lines start one column past the paren... keeps the assignment '=' from blending in with all the '=='
Yeah, that line could be *much* clearer. I've put parens around the whole expression. Are parens around equality/inequality tests preferred as well? I've seen cases in the codebase.
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/scoreboard.cc, line 164
<http://reviews.gem5.org/r/2279/diff/1/?file=39857#file39857line164>
space after for
Yep
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/scoreboard.cc, line 238
<http://reviews.gem5.org/r/2279/diff/1/?file=39857#file39857line238>
opening brace at end of previous line (here & a few places below)
There are lots of those. They're following the explicitly allowable case where the condition is longer than a line.

There may be some wild cases left where a modified condition *does* now fit on the line but may still be split (for unjustifiable reasons) but I've spent quite a bit of time cleaning those before the patch was submitted.
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 67
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line67>
We also have various objects that have dump() or print() methods... it would be nice to standardize this
Actually, report is specifically used here for MinorTrace. Its name possibly should reflect just that. Maybe Ticked should have been be MinorTicked? ...::report should almost certainly really be ...::minorTrace to reflect this specialised use.

I think there are three interesting opportunities here:

1) Standardise a name/maybe some flags for micro-architectural dumping
2) Standardise a format for human-readable dump
3) Standardise a format for machine-readable dump

MinorTrace is horribly verbose but a it's a crack at doing point 3.
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 74
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line74>
integrating with ClockedObject would eliminate the multiple inheritance... not that MI is totally evil, but it's always better to avoid it when possible
I think I've answered that one above.
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 60
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line60>
This seems like it could be useful outside of Minor... perhaps we should put it in src/sim, or even just integrate this functionality with ClockedObject
Yes, the 'evaluate' member function on Ticked could be hoisted up to ClockedObject. The cycle accounting in TickedModule could potentially also go that way. I didn't make that change as I didn't want to try and have the interface blessed/promoted by trying to affect a core class (and set precedent and pass the tighter review that that demands).

You can see, in Ticked, my preference for building 'interface'-like classes and using multiple inheritance for interface-link classes.
In this case, Ticked isn't used (any more, it was previously) in contexts where the 'virtual' qualification on its member functions is used anymore, so arguably it isn't really functioning as a base class anymore.

I would suggest dropping Ticked and just folding its member functions into Stage and TickedModule. (I don't believe 'Ticked */&' is ever used)
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/trace.hh, line 63
<http://reviews.gem5.org/r/2279/diff/1/?file=39862#file39862line63>
This would be very useful outside of Minor... should go in src/base/trace.hh, IMO
Yes, it would and it could be used to clean up some of annoying ambiguities around DPRINTF use and maybe even replace the DPRINTF macros with functions.

Using Named to replace _name/name in SimObject would sort of open up the interface-like MI question. (Named isn't actually an interface as it has a data member).

I suggest moving Named into src/base/trace.hh so it can be optionally used, but not go as far as trying to strongly suggest its usage by making SimObject adopt it. Thoughts?
Post by Ali Saidi via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/static_inst.hh, line 66
<http://reviews.gem5.org/r/2279/diff/1/?file=39864#file39864line66>
blank line here would be nice
Before SymbolTable? Yes.

A small style question: What's should be the preferred form for namespaces? I've seen both brace location options used and I've gone with next-line braces for all uses of namespaces as they are large scale structures. The use of namespace in static_inst.hh is really just a fancy (and unfortunately required) way of building a reference to a class, should putting the brace on the same line be the preferred form for this one-liner? (As with Trace::InstRecord). If this isn't already in the style guide, maybe it should be.


- Andrew


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5125
-----------------------------------------------------------
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated May 30, 2014, 3:23 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/cpu/minor/Expr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/expr.hh PRE-CREATION
src/cpu/minor/expr.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Andrew Bardsley via gem5-dev
2014-06-18 08:38:02 UTC
Permalink
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/Expr.py, line 48
<http://reviews.gem5.org/r/2279/diff/1/?file=39827#file39827line48>
This is pretty interesting... it would be nice to generalize this capability and not make it Minor-specific
Yeah. MinorExpr could easily be hoisted upwards and lose its Minor prefix (It doesn't have any dependencies on Minor).
Maybe TimingExpr or something like that (to disambiguate and suggest its function a bit more) would be a good name?
In r2: I've moved Minor::Expr up to be in src/cpu as TimingExpr
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 60
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line60>
This seems like it could be useful outside of Minor... perhaps we should put it in src/sim, or even just integrate this functionality with ClockedObject
Yes, the 'evaluate' member function on Ticked could be hoisted up to ClockedObject. The cycle accounting in TickedModule could potentially also go that way. I didn't make that change as I didn't want to try and have the interface blessed/promoted by trying to affect a core class (and set precedent and pass the tighter review that that demands).
You can see, in Ticked, my preference for building 'interface'-like classes and using multiple inheritance for interface-link classes.
In this case, Ticked isn't used (any more, it was previously) in contexts where the 'virtual' qualification on its member functions is used anymore, so arguably it isn't really functioning as a base class anymore.
I would suggest dropping Ticked and just folding its member functions into Stage and TickedModule. (I don't believe 'Ticked */&' is ever used)
In r2: In the end I didn't remove Ticked. It felt wrong to remove such an obviously 'base'/interface definition.
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 67
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line67>
We also have various objects that have dump() or print() methods... it would be nice to standardize this
Actually, report is specifically used here for MinorTrace. Its name possibly should reflect just that. Maybe Ticked should have been be MinorTicked? ...::report should almost certainly really be ...::minorTrace to reflect this specialised use.
1) Standardise a name/maybe some flags for micro-architectural dumping
2) Standardise a format for human-readable dump
3) Standardise a format for machine-readable dump
MinorTrace is horribly verbose but a it's a crack at doing point 3.
In r2: I've renamed 'report' to 'minorTrace' to reflect its very specific role in Minor.
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/ticked.hh, line 74
<http://reviews.gem5.org/r/2279/diff/1/?file=39861#file39861line74>
integrating with ClockedObject would eliminate the multiple inheritance... not that MI is totally evil, but it's always better to avoid it when possible
I think I've answered that one above.
In r2: see above
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/trace.hh, line 63
<http://reviews.gem5.org/r/2279/diff/1/?file=39862#file39862line63>
This would be very useful outside of Minor... should go in src/base/trace.hh, IMO
Yes, it would and it could be used to clean up some of annoying ambiguities around DPRINTF use and maybe even replace the DPRINTF macros with functions.
Using Named to replace _name/name in SimObject would sort of open up the interface-like MI question. (Named isn't actually an interface as it has a data member).
I suggest moving Named into src/base/trace.hh so it can be optionally used, but not go as far as trying to strongly suggest its usage by making SimObject adopt it. Thoughts?
In r2: I've moved Named into src/base/trace.hh as another convenience definition (alongside StringWrap).


- Andrew


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5125
-----------------------------------------------------------
Post by Andrew Bardsley via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Steve Reinhardt via gem5-dev
2014-07-01 18:05:51 UTC
Permalink
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/minor/cpu.hh, line 88
<http://reviews.gem5.org/r/2279/diff/1/?file=39833#file39833line88>
I don't know why, and I know it's not in the style guide, but all the gem5 code I've seen (or written) has the colon at the beginning of the second line, not the end of the first... might as well be consistent
'^ * : [a-z]' (next line :) 257 lines
'\) :'$ (trailing :) 394 lines
next line: 231 lines
trailing: 125 lines
So next line seems to be winning.
I have no real preference.
Do you want to add this to the style guide?
Hmm, I get significantly different numbers:

% find src -type f | xargs grep ') :$' | wc -l
321
% find src -type f | xargs grep '^ * : \w' | wc -l
859
% find src -type f | xargs grep ') :$' | grep -v '^src/arch/' | wc -l
53
% find src -type f | xargs grep '^ * : \w' | grep -v '^src/arch/' | wc -l
618

So not counting src/arch, it's pretty overwhelming in favor of next line. I'd be fine with standardizing on that, but I don't know if anyone else cares.

And just for grins....

% find src -type f | xargs grep ') :$' | grep '^src/arch/' | perl -ne '@F = split("/"); print $F[2], "\n";' | uniq -c
1 alpha
28 sparc
134 arm
84 x86
19 mips
2 generic


- Steve


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5125
-----------------------------------------------------------
Post by Andrew Bardsley via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 10:03 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Steve Reinhardt via gem5-dev
2014-07-01 18:28:29 UTC
Permalink
Post by Andrew Bardsley via gem5-dev
Post by Steve Reinhardt via gem5-dev
src/cpu/static_inst.hh, line 66
<http://reviews.gem5.org/r/2279/diff/1/?file=39864#file39864line66>
blank line here would be nice
Before SymbolTable? Yes.
A small style question: What's should be the preferred form for namespaces? I've seen both brace location options used and I've gone with next-line braces for all uses of namespaces as they are large scale structures. The use of namespace in static_inst.hh is really just a fancy (and unfortunately required) way of building a reference to a class, should putting the brace on the same line be the preferred form for this one-liner? (As with Trace::InstRecord). If this isn't already in the style guide, maybe it should be.
Good questions. I don't have a strong opinion. Arguably we always put the opening brace on a separate line for other top-level block constructs (class and function definitions) so I'd lean towards saying that namespaces should do the same for consistency. I'm open to other arguments though. Whatever we come up with, it probably should go in the style guide.


- Steve


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5125
-----------------------------------------------------------
Post by Andrew Bardsley via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 10:03 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Korey Sewell via gem5-dev
2014-06-05 10:28:37 UTC
Permalink
Hi All,
I won't to get to review this until next week at the earliest, but I think
this is good progress here and a definite step in the right direction.

I'd actually be in favor of just eventually renaming "Minor" to "InOrder"
long term. I'm unable to guarantee the same level of maintenance (for
InoRder) that the ARM guys have done for Minor so to me a deprecation
process makes sense.

The issue with deprecating immediately is support for other other ISAs and
things like that but again I just wanted to say I support this effort and
will get to a review next week :)

-Korey
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/cpu/minor/Expr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/expr.hh PRE-CREATION
src/cpu/minor/expr.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
--
- Korey
Ali Saidi via gem5-dev
2014-06-17 17:03:47 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------

(Updated June 17, 2014, 5:03 p.m.)


Review request for Default.


Repository: gem5


Description
-------

Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036


Diffs (updated)
-----

build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION

Diff: http://reviews.gem5.org/r/2279/diff/


Testing
-------

Boots Linux and runs regression tests for ALPHA and ARM.


Thanks,

Ali Saidi
Ali Saidi via gem5-dev
2014-07-01 14:01:53 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------


Last chance for comments?

- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Steve Reinhardt via gem5-dev
2014-07-01 16:55:11 UTC
Permalink
Give me a chance... I haven't had time to go over Andrew's responses
carefully.

I appreciate the changes you've made so far, Andrew. I'm still not
convinced that Ticked needs to be a separate class though. What's the
point of an interface class when the only use of the interface is in
conjunction with a specific implementation? Also, what does minorReport()
have to do with evaluate()? It's not clear why these are part of the same
interface.

All of the methods in TickedModule look like they would be generally useful
outside of Minor. Even if existing ClockedModules don't use them, they
could migrate to use them eventually. And certainly the TickedModule
methods could be useful outside of Minor. If we really think that the few
extra fields in TickedModule are a burden, we could just make TickedModule
derive from ClockedModule (but still push it up into src/sim).

One question I don't know the answer to: are there any ClockedModule
instances that would *not* find the TickedModule features useful? I think
there is an argument for making these features "standard" across all
ClockedModule instances.

So how about this proposal:

- Get rid of the Ticked interface class, and either (1) integrate the
TickedModule features into ClockedModule or (2) add TickedModule as a
derived class in src/sim.

- Create a MinorModule class that derives from ClockedModule or
TickedModule (depending on which way we go above) that adds the virtual
minorReport() method.

- Everything in Minor that currently derives from TickedModule can derive
from MinorModule and won't know the difference.

Thoughts?

Steve
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------
Last chance for comments?
- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
Andrew Bardsley via gem5-dev
2014-07-01 17:33:42 UTC
Permalink
Only slight modification to your proposal:

How about I get rid of Ticked and flatten evaluate/minorTrace into the classes which need it.
I think that there aren't actually any cases where there need to be virtual calls to any of
its member functions.

I assume that by ClockedModule you mean ClockedObject everywhere?

I'll make a TickedObject derived class from ClockedObject that's the same as the current
TickedModule but with 'evaluate' and move that into sim/src

I'll not bother with a base-classed 'minorTrace' as I believe all the calls have explicitly
known types anyway. minorTrace will appear on Pipeline.

Pipeline will be (as it is now) the single instance of TickedObject in Minor.

- Andrew

-----Original Message-----
From: gem5-dev [mailto:gem5-dev-bounces-1Gs4CP2/***@public.gmane.org] On Behalf Of Steve Reinhardt via gem5-dev
Sent: 01 July 2014 17:55
To: gem5 Developer List
Cc: Ali Saidi
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model

Give me a chance... I haven't had time to go over Andrew's responses
carefully.

I appreciate the changes you've made so far, Andrew. I'm still not
convinced that Ticked needs to be a separate class though. What's the
point of an interface class when the only use of the interface is in
conjunction with a specific implementation? Also, what does minorReport()
have to do with evaluate()? It's not clear why these are part of the same
interface.

All of the methods in TickedModule look like they would be generally useful
outside of Minor. Even if existing ClockedModules don't use them, they
could migrate to use them eventually. And certainly the TickedModule
methods could be useful outside of Minor. If we really think that the few
extra fields in TickedModule are a burden, we could just make TickedModule
derive from ClockedModule (but still push it up into src/sim).

One question I don't know the answer to: are there any ClockedModule
instances that would *not* find the TickedModule features useful? I think
there is an argument for making these features "standard" across all
ClockedModule instances.

So how about this proposal:

- Get rid of the Ticked interface class, and either (1) integrate the
TickedModule features into ClockedModule or (2) add TickedModule as a
derived class in src/sim.

- Create a MinorModule class that derives from ClockedModule or
TickedModule (depending on which way we go above) that adds the virtual
minorReport() method.

- Everything in Minor that currently derives from TickedModule can derive
from MinorModule and won't know the difference.

Thoughts?

Steve
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------
Last chance for comments?
- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
gem5-dev-1Gs4CP2/***@public.gmane.org
http://m5sim.org/mailman/listinfo/gem5-dev


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Steve Reinhardt via gem5-dev
2014-07-01 17:44:24 UTC
Permalink
Yes, ClockedObject, sorry. I got thrown off by TickedModule.

Your proposal sounds great to me. Thanks a lot for being flexible.

Steve


On Tue, Jul 1, 2014 at 10:33 AM, Andrew Bardsley via gem5-dev <
Post by Andrew Bardsley via gem5-dev
How about I get rid of Ticked and flatten evaluate/minorTrace into the
classes which need it.
I think that there aren't actually any cases where there need to be virtual calls to any of
its member functions.
I assume that by ClockedModule you mean ClockedObject everywhere?
I'll make a TickedObject derived class from ClockedObject that's the same as the current
TickedModule but with 'evaluate' and move that into sim/src
I'll not bother with a base-classed 'minorTrace' as I believe all the calls have explicitly
known types anyway. minorTrace will appear on Pipeline.
Pipeline will be (as it is now) the single instance of TickedObject in Minor.
- Andrew
-----Original Message-----
Reinhardt via gem5-dev
Sent: 01 July 2014 17:55
To: gem5 Developer List
Cc: Ali Saidi
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model
Give me a chance... I haven't had time to go over Andrew's responses
carefully.
I appreciate the changes you've made so far, Andrew. I'm still not
convinced that Ticked needs to be a separate class though. What's the
point of an interface class when the only use of the interface is in
conjunction with a specific implementation? Also, what does minorReport()
have to do with evaluate()? It's not clear why these are part of the same
interface.
All of the methods in TickedModule look like they would be generally useful
outside of Minor. Even if existing ClockedModules don't use them, they
could migrate to use them eventually. And certainly the TickedModule
methods could be useful outside of Minor. If we really think that the few
extra fields in TickedModule are a burden, we could just make TickedModule
derive from ClockedModule (but still push it up into src/sim).
One question I don't know the answer to: are there any ClockedModule
instances that would *not* find the TickedModule features useful? I think
there is an argument for making these features "standard" across all
ClockedModule instances.
- Get rid of the Ticked interface class, and either (1) integrate the
TickedModule features into ClockedModule or (2) add TickedModule as a
derived class in src/sim.
- Create a MinorModule class that derives from ClockedModule or
TickedModule (depending on which way we go above) that adds the virtual
minorReport() method.
- Everything in Minor that currently derives from TickedModule can derive
from MinorModule and won't know the difference.
Thoughts?
Steve
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------
Last chance for comments?
- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen
Post by Ali Saidi via gem5-dev
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
Andreas Hansson via gem5-dev
2014-07-01 17:46:25 UTC
Permalink
Hi Steve,

Just to chime in here. There are definitely objects that are clocked and
not ticked. Thus, as Andrew already suggested, the most sensible thing to
do is derive TickedObject from ClockedObject.

Andreas
Post by Steve Reinhardt via gem5-dev
Yes, ClockedObject, sorry. I got thrown off by TickedModule.
Your proposal sounds great to me. Thanks a lot for being flexible.
Steve
On Tue, Jul 1, 2014 at 10:33 AM, Andrew Bardsley via gem5-dev <
Post by Andrew Bardsley via gem5-dev
How about I get rid of Ticked and flatten evaluate/minorTrace into the
classes which need it.
I think that there aren't actually any cases where there need to be
virtual calls to any of
its member functions.
I assume that by ClockedModule you mean ClockedObject everywhere?
I'll make a TickedObject derived class from ClockedObject that's the
same
as the current
TickedModule but with 'evaluate' and move that into sim/src
I'll not bother with a base-classed 'minorTrace' as I believe all the
calls have explicitly
known types anyway. minorTrace will appear on Pipeline.
Pipeline will be (as it is now) the single instance of TickedObject in Minor.
- Andrew
-----Original Message-----
Reinhardt via gem5-dev
Sent: 01 July 2014 17:55
To: gem5 Developer List
Cc: Ali Saidi
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model
Give me a chance... I haven't had time to go over Andrew's responses
carefully.
I appreciate the changes you've made so far, Andrew. I'm still not
convinced that Ticked needs to be a separate class though. What's the
point of an interface class when the only use of the interface is in
conjunction with a specific implementation? Also, what does
minorReport()
have to do with evaluate()? It's not clear why these are part of the same
interface.
All of the methods in TickedModule look like they would be generally useful
outside of Minor. Even if existing ClockedModules don't use them, they
could migrate to use them eventually. And certainly the TickedModule
methods could be useful outside of Minor. If we really think that the few
extra fields in TickedModule are a burden, we could just make
TickedModule
derive from ClockedModule (but still push it up into src/sim).
One question I don't know the answer to: are there any ClockedModule
instances that would *not* find the TickedModule features useful? I think
there is an argument for making these features "standard" across all
ClockedModule instances.
- Get rid of the Ticked interface class, and either (1) integrate the
TickedModule features into ClockedModule or (2) add TickedModule as a
derived class in src/sim.
- Create a MinorModule class that derives from ClockedModule or
TickedModule (depending on which way we go above) that adds the virtual
minorReport() method.
- Everything in Minor that currently derives from TickedModule can derive
from MinorModule and won't know the difference.
Thoughts?
Steve
On Tue, Jul 1, 2014 at 7:01 AM, Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------
Last chance for comments?
- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a
four
Post by Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including
Linux
Post by Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen
Post by Ali Saidi via gem5-dev
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Andrew Bardsley via gem5-dev
2014-07-14 09:06:47 UTC
Permalink
OK, Steve. There's a new Minor patch up on the board.

I've kept a 'Ticked' class but now it just hosts all the TickedObject functionality so that it can be added to objects which are already SimObjects/don't want to be SimObjects. A TickedObject class brings Ticked and SimObject together. A little internal review has led to moving some of the stats handling around and making making Ticked own a few key stats and (possibly) sync with an external numCycles.

I've snuck in a couple of other fixup patches with this one which should explain other changes between versions.

- Andrew

-----Original Message-----
From: gem5-dev [mailto:gem5-dev-bounces-1Gs4CP2/***@public.gmane.org] On Behalf Of Andreas Hansson via gem5-dev
Sent: 01 July 2014 18:46
To: gem5 Developer List
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model

Hi Steve,

Just to chime in here. There are definitely objects that are clocked and
not ticked. Thus, as Andrew already suggested, the most sensible thing to
do is derive TickedObject from ClockedObject.

Andreas
Post by Steve Reinhardt via gem5-dev
Yes, ClockedObject, sorry. I got thrown off by TickedModule.
Your proposal sounds great to me. Thanks a lot for being flexible.
Steve
On Tue, Jul 1, 2014 at 10:33 AM, Andrew Bardsley via gem5-dev <
Post by Andrew Bardsley via gem5-dev
How about I get rid of Ticked and flatten evaluate/minorTrace into the
classes which need it.
I think that there aren't actually any cases where there need to be
virtual calls to any of
its member functions.
I assume that by ClockedModule you mean ClockedObject everywhere?
I'll make a TickedObject derived class from ClockedObject that's the
same
as the current
TickedModule but with 'evaluate' and move that into sim/src
I'll not bother with a base-classed 'minorTrace' as I believe all the
calls have explicitly
known types anyway. minorTrace will appear on Pipeline.
Pipeline will be (as it is now) the single instance of TickedObject in Minor.
- Andrew
-----Original Message-----
Reinhardt via gem5-dev
Sent: 01 July 2014 17:55
To: gem5 Developer List
Cc: Ali Saidi
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model
Give me a chance... I haven't had time to go over Andrew's responses
carefully.
I appreciate the changes you've made so far, Andrew. I'm still not
convinced that Ticked needs to be a separate class though. What's the
point of an interface class when the only use of the interface is in
conjunction with a specific implementation? Also, what does
minorReport()
have to do with evaluate()? It's not clear why these are part of the same
interface.
All of the methods in TickedModule look like they would be generally useful
outside of Minor. Even if existing ClockedModules don't use them, they
could migrate to use them eventually. And certainly the TickedModule
methods could be useful outside of Minor. If we really think that the few
extra fields in TickedModule are a burden, we could just make
TickedModule
derive from ClockedModule (but still push it up into src/sim).
One question I don't know the answer to: are there any ClockedModule
instances that would *not* find the TickedModule features useful? I think
there is an argument for making these features "standard" across all
ClockedModule instances.
- Get rid of the Ticked interface class, and either (1) integrate the
TickedModule features into ClockedModule or (2) add TickedModule as a
derived class in src/sim.
- Create a MinorModule class that derives from ClockedModule or
TickedModule (depending on which way we go above) that adds the virtual
minorReport() method.
- Everything in Minor that currently derives from TickedModule can derive
from MinorModule and won't know the difference.
Thoughts?
Steve
On Tue, Jul 1, 2014 at 7:01 AM, Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5171
-----------------------------------------------------------
Last chance for comments?
- Ali Saidi
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated June 17, 2014, 5:03 p.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a
four
Post by Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including
Linux
Post by Ali Saidi via gem5-dev
Post by Ali Saidi via gem5-dev
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen
Post by Ali Saidi via gem5-dev
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
build_opts/ALPHA a2bb75a474fd
build_opts/ARM a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
src/base/trace.hh a2bb75a474fd
src/cpu/SConscript a2bb75a474fd
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/stage.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/ticked.hh PRE-CREATION
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/doc/inside-minor.doxygen PRE-CREATION
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-dev mailing list
gem5-dev-1Gs4CP2/***@public.gmane.org
http://m5sim.org/mailman/listinfo/gem5-dev


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ali Saidi via gem5-dev
2014-07-11 14:32:56 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------

(Updated July 11, 2014, 2:32 p.m.)


Review request for Default.


Repository: gem5


Description
-------

Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036


Diffs (updated)
-----

src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION

Diff: http://reviews.gem5.org/r/2279/diff/


Testing
-------

Boots Linux and runs regression tests for ALPHA and ARM.


Thanks,

Ali Saidi
Steve Reinhardt via gem5-dev
2014-07-20 23:23:30 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------

Ship it!


Looks good, thanks for all the changes.

One question: in your email you said that Ticked was separate so it could be "added to objects which are already SimObjects/don't want to be SimObjects". I get the latter, but in the former case, is there a reason not to just make those objects derive from TickedObject now?

- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
Korey Sewell via gem5-dev
2014-07-21 07:49:32 UTC
Permalink
Hey folks,
It looks like the Minor CPU model is all but a click away from check-in,
which is great!

Overall, I'm still not convinced that you don't just want to call the model
"InOrder" and rename the previous inorder to something else prior to
deprecation.

The prior point isn't necessarily a blocking issue, but do we have an
overall direction there? Do I need to commit some time to help with that?
If so, let me know.

-Korey



On Sun, Jul 20, 2014 at 4:23 PM, Steve Reinhardt via gem5-dev <
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------
Ship it!
Looks good, thanks for all the changes.
One question: in your email you said that Ticked was separate so it could
be "added to objects which are already SimObjects/don't want to be
SimObjects". I get the latter, but in the former case, is there a reason
not to just make those objects derive from TickedObject now?
- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
--
- Korey
Andreas Hansson via gem5-dev
2014-07-21 07:53:48 UTC
Permalink
Hi Korey,

Our proposed plan of action is to push this as is, let the user-base give
it a spin, and once there is consensus deprecate the old in-order model
and rename Minor -> In-Order. Once we are at that point it would also be
good to understand the pros/cons of keeping the old code. From a
code-maintenance point of view I¹d rather there was a single in-order
model in the long run. I hope that makes sense.

Andreas
Post by Korey Sewell via gem5-dev
Hey folks,
It looks like the Minor CPU model is all but a click away from check-in,
which is great!
Overall, I'm still not convinced that you don't just want to call the model
"InOrder" and rename the previous inorder to something else prior to
deprecation.
The prior point isn't necessarily a blocking issue, but do we have an
overall direction there? Do I need to commit some time to help with that?
If so, let me know.
-Korey
On Sun, Jul 20, 2014 at 4:23 PM, Steve Reinhardt via gem5-dev <
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------
Ship it!
Looks good, thanks for all the changes.
One question: in your email you said that Ticked was separate so it could
be "added to objects which are already SimObjects/don't want to be
SimObjects". I get the latter, but in the former case, is there a reason
not to just make those objects derive from TickedObject now?
- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
--
- Korey
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Korey Sewell via gem5-dev
2014-07-21 08:28:47 UTC
Permalink
HI Andreas,

Yes, I'd subscribe to that train of thought. Thanks for the quick response.

I try to "peek my head in" whenever I see "InOrder" changes/questions on
the gem5 list so please let me know when/where I can be of assistance when
the time comes.

Korey



On Mon, Jul 21, 2014 at 12:53 AM, Andreas Hansson via gem5-dev <
Post by Andreas Hansson via gem5-dev
Hi Korey,
Our proposed plan of action is to push this as is, let the user-base give
it a spin, and once there is consensus deprecate the old in-order model
and rename Minor -> In-Order. Once we are at that point it would also be
good to understand the pros/cons of keeping the old code. From a
code-maintenance point of view I¹d rather there was a single in-order
model in the long run. I hope that makes sense.
Andreas
Post by Korey Sewell via gem5-dev
Hey folks,
It looks like the Minor CPU model is all but a click away from check-in,
which is great!
Overall, I'm still not convinced that you don't just want to call the model
"InOrder" and rename the previous inorder to something else prior to
deprecation.
The prior point isn't necessarily a blocking issue, but do we have an
overall direction there? Do I need to commit some time to help with that?
If so, let me know.
-Korey
On Sun, Jul 20, 2014 at 4:23 PM, Steve Reinhardt via gem5-dev <
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------
Ship it!
Looks good, thanks for all the changes.
One question: in your email you said that Ticked was separate so it could
be "added to objects which are already SimObjects/don't want to be
SimObjects". I get the latter, but in the former case, is there a reason
not to just make those objects derive from TickedObject now?
- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
--
- Korey
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
--
- Korey
Andrew Bardsley via gem5-dev
2014-07-21 10:18:29 UTC
Permalink
Those objects could derive from TickedObject, yes. Although Minor itself could be an example of the later class of use if I'd attached the Ticked interface to MinorCPU rather than the container/abstracting Pipeline object (not a SimObject). MinorCPU would need to be derived from BaseCPU and TickedObject but that would have made it inherit from SimObject in two ways and so required virtual base classes (eek). Migrating BaseCPU to be derived from TickedObject in the future would, naturally, solve that problem.

Quite separately, the former (non SimObject) use case for Ticked could still remain useful even after that point as, personally, I quite like the pimpl-ish separation of Pipeline and MinorCPU.

- Andrew

-----Original Message-----
From: gem5-dev [mailto:gem5-dev-bounces-1Gs4CP2/***@public.gmane.org] On Behalf Of Steve Reinhardt via gem5-dev
Sent: 21 July 2014 00:24
To: Steve Reinhardt; Ali Saidi; Default
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------

Ship it!


Looks good, thanks for all the changes.

One question: in your email you said that Ticked was separate so it could be "added to objects which are already SimObjects/don't want to be SimObjects". I get the latter, but in the former case, is there a reason not to just make those objects derive from TickedObject now?

- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
gem5-dev-1Gs4CP2/***@public.gmane.org
http://m5sim.org/mailman/listinfo/gem5-dev


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Steve Reinhardt via gem5-dev
2014-07-21 13:42:28 UTC
Permalink
I see the value in having Ticked as a separate mix-in so it can apply to
non-SimObjects; no argument there. I hadn't thought of the
virtual-inheritance-avoidance aspect for SimObjects, but it's a very good
rational as well.

Steve


On Mon, Jul 21, 2014 at 3:18 AM, Andrew Bardsley via gem5-dev <
Post by Andrew Bardsley via gem5-dev
Those objects could derive from TickedObject, yes. Although Minor itself
could be an example of the later class of use if I'd attached the Ticked
interface to MinorCPU rather than the container/abstracting Pipeline object
(not a SimObject). MinorCPU would need to be derived from BaseCPU and
TickedObject but that would have made it inherit from SimObject in two ways
and so required virtual base classes (eek). Migrating BaseCPU to be
derived from TickedObject in the future would, naturally, solve that
problem.
Quite separately, the former (non SimObject) use case for Ticked could
still remain useful even after that point as, personally, I quite like the
pimpl-ish separation of Pipeline and MinorCPU.
- Andrew
-----Original Message-----
Reinhardt via gem5-dev
Sent: 21 July 2014 00:24
To: Steve Reinhardt; Ali Saidi; Default
Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU model
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/#review5215
-----------------------------------------------------------
Ship it!
Looks good, thanks for all the changes.
One question: in your email you said that Ticked was separate so it could
be "added to objects which are already SimObjects/don't want to be
SimObjects". I get the latter, but in the former case, is there a reason
not to just make those objects derive from TickedObject now?
- Steve Reinhardt
Post by Ali Saidi via gem5-dev
-----------------------------------------------------------
http://reviews.gem5.org/r/2279/
-----------------------------------------------------------
(Updated July 11, 2014, 7:32 a.m.)
Review request for Default.
Repository: gem5
Description
-------
Changeset 10237:5794a56b79c4
---------------------------
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in src/doc/inside-minor.doxygen
and
Post by Ali Saidi via gem5-dev
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
Diffs
-----
src/sim/ticked_object.cc PRE-CREATION
src/sim/ticked_object.hh PRE-CREATION
src/sim/TickedObject.py PRE-CREATION
src/sim/SConscript a2bb75a474fd
src/doc/inside-minor.doxygen PRE-CREATION
src/cpu/timing_expr.cc PRE-CREATION
src/cpu/timing_expr.hh PRE-CREATION
src/cpu/static_inst.hh a2bb75a474fd
src/cpu/pred/SConscript a2bb75a474fd
src/cpu/minor/trace.hh PRE-CREATION
src/cpu/minor/stats.hh PRE-CREATION
src/cpu/minor/stats.cc PRE-CREATION
src/cpu/minor/scoreboard.cc PRE-CREATION
src/cpu/minor/scoreboard.hh PRE-CREATION
src/cpu/minor/pipeline.cc PRE-CREATION
src/cpu/minor/pipeline.hh PRE-CREATION
src/cpu/minor/pipe_data.cc PRE-CREATION
src/cpu/minor/pipe_data.hh PRE-CREATION
src/cpu/minor/lsq.cc PRE-CREATION
src/cpu/minor/lsq.hh PRE-CREATION
src/cpu/minor/func_unit.cc PRE-CREATION
src/cpu/minor/func_unit.hh PRE-CREATION
src/cpu/minor/fetch2.cc PRE-CREATION
src/cpu/minor/fetch2.hh PRE-CREATION
src/cpu/minor/fetch1.cc PRE-CREATION
src/cpu/minor/fetch1.hh PRE-CREATION
src/cpu/minor/execute.cc PRE-CREATION
src/cpu/minor/execute.hh PRE-CREATION
src/cpu/minor/exec_context.hh PRE-CREATION
src/cpu/minor/dyn_inst.cc PRE-CREATION
src/cpu/minor/dyn_inst.hh PRE-CREATION
src/cpu/minor/decode.cc PRE-CREATION
src/cpu/minor/cpu.cc PRE-CREATION
src/cpu/minor/decode.hh PRE-CREATION
src/cpu/minor/cpu.hh PRE-CREATION
src/cpu/minor/buffers.hh PRE-CREATION
src/cpu/minor/activity.cc PRE-CREATION
src/cpu/minor/activity.hh PRE-CREATION
src/cpu/minor/SConsopts PRE-CREATION
src/cpu/minor/MinorCPU.py PRE-CREATION
src/cpu/minor/SConscript PRE-CREATION
src/cpu/TimingExpr.py PRE-CREATION
src/cpu/SConscript a2bb75a474fd
src/base/trace.hh a2bb75a474fd
configs/common/CpuConfig.py a2bb75a474fd
build_opts/ARM a2bb75a474fd
build_opts/ALPHA a2bb75a474fd
util/minorview.py PRE-CREATION
util/minorview/__init__.py PRE-CREATION
util/minorview/blobs.py PRE-CREATION
util/minorview/colours.py PRE-CREATION
util/minorview/minor.pic PRE-CREATION
util/minorview/model.py PRE-CREATION
util/minorview/parse.py PRE-CREATION
util/minorview/point.py PRE-CREATION
util/minorview/view.py PRE-CREATION
Diff: http://reviews.gem5.org/r/2279/diff/
Testing
-------
Boots Linux and runs regression tests for ALPHA and ARM.
Thanks,
Ali Saidi
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-dev mailing list
http://m5sim.org/mailman/listinfo/gem5-dev
Loading...