Discussion:
[gem5-dev] Review Request: MEM: Add port proxies instead of non-structural ports
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Andreas Hansson
2011-12-19 13:54:17 UTC
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Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

This is a complete re-make of the previous patches taking all the
feedback into account.

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs
-----

configs/common/FSConfig.py ca98021c3f96
configs/ruby/Ruby.py ca98021c3f96
src/arch/alpha/freebsd/system.cc ca98021c3f96
src/arch/alpha/linux/process.cc ca98021c3f96
src/arch/alpha/linux/system.hh ca98021c3f96
src/arch/alpha/linux/system.cc ca98021c3f96
src/arch/alpha/linux/threadinfo.hh ca98021c3f96
src/arch/alpha/remote_gdb.cc ca98021c3f96
src/arch/alpha/stacktrace.cc ca98021c3f96
src/arch/alpha/system.hh ca98021c3f96
src/arch/alpha/system.cc ca98021c3f96
src/arch/alpha/tru64/process.cc ca98021c3f96
src/arch/alpha/tru64/system.cc ca98021c3f96
src/arch/alpha/utility.cc ca98021c3f96
src/arch/alpha/vtophys.hh ca98021c3f96
src/arch/alpha/vtophys.cc ca98021c3f96
src/arch/arm/linux/process.cc ca98021c3f96
src/arch/arm/linux/system.cc ca98021c3f96
src/arch/arm/process.cc ca98021c3f96
src/arch/arm/stacktrace.cc ca98021c3f96
src/arch/arm/system.hh ca98021c3f96
src/arch/arm/system.cc ca98021c3f96
src/arch/arm/utility.cc ca98021c3f96
src/arch/arm/vtophys.cc ca98021c3f96
src/arch/mips/linux/process.cc ca98021c3f96
src/arch/mips/linux/system.cc ca98021c3f96
src/arch/mips/linux/threadinfo.hh ca98021c3f96
src/arch/mips/stacktrace.cc ca98021c3f96
src/arch/mips/utility.cc ca98021c3f96
src/arch/power/linux/process.cc ca98021c3f96
src/arch/power/process.cc ca98021c3f96
src/arch/sparc/linux/syscalls.cc ca98021c3f96
src/arch/sparc/process.cc ca98021c3f96
src/arch/sparc/solaris/process.cc ca98021c3f96
src/arch/sparc/utility.cc ca98021c3f96
src/arch/sparc/vtophys.cc ca98021c3f96
src/arch/x86/bios/intelmp.hh ca98021c3f96
src/arch/x86/bios/intelmp.cc ca98021c3f96
src/arch/x86/bios/smbios.hh ca98021c3f96
src/arch/x86/bios/smbios.cc ca98021c3f96
src/arch/x86/linux/syscalls.cc ca98021c3f96
src/arch/x86/linux/system.cc ca98021c3f96
src/arch/x86/process.cc ca98021c3f96
src/arch/x86/stacktrace.cc ca98021c3f96
src/arch/x86/system.cc ca98021c3f96
src/base/loader/elf_object.hh ca98021c3f96
src/base/loader/elf_object.cc ca98021c3f96
src/base/loader/hex_file.hh ca98021c3f96
src/base/loader/hex_file.cc ca98021c3f96
src/base/loader/object_file.hh ca98021c3f96
src/base/loader/object_file.cc ca98021c3f96
src/base/remote_gdb.cc ca98021c3f96
src/cpu/checker/thread_context.hh ca98021c3f96
src/cpu/inorder/cpu.cc ca98021c3f96
src/cpu/inorder/thread_context.hh ca98021c3f96
src/cpu/inorder/thread_context.cc ca98021c3f96
src/cpu/o3/thread_context.hh ca98021c3f96
src/cpu/o3/thread_context_impl.hh ca98021c3f96
src/cpu/ozone/cpu.hh ca98021c3f96
src/cpu/ozone/cpu_impl.hh ca98021c3f96
src/cpu/simple_thread.hh ca98021c3f96
src/cpu/simple_thread.cc ca98021c3f96
src/cpu/thread_context.hh ca98021c3f96
src/cpu/thread_state.hh ca98021c3f96
src/cpu/thread_state.cc ca98021c3f96
src/dev/simple_disk.cc ca98021c3f96
src/kern/tru64/tru64.hh ca98021c3f96
src/kern/tru64/tru64_events.cc ca98021c3f96
src/mem/SConscript ca98021c3f96
src/mem/bus.cc ca98021c3f96
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh ca98021c3f96
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc ca98021c3f96
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript ca98021c3f96
src/mem/ruby/system/Sequencer.py ca98021c3f96
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh ca98021c3f96
src/mem/translating_port.cc ca98021c3f96
src/mem/vport.hh ca98021c3f96
src/mem/vport.cc ca98021c3f96
src/sim/arguments.hh ca98021c3f96
src/sim/process.hh ca98021c3f96
src/sim/process.cc ca98021c3f96
src/sim/process_impl.hh ca98021c3f96
src/sim/syscall_emul.hh ca98021c3f96
src/sim/syscall_emul.cc ca98021c3f96
src/sim/system.hh ca98021c3f96
src/sim/system.cc ca98021c3f96
src/sim/vptr.hh ca98021c3f96
tests/configs/inorder-timing.py ca98021c3f96
tests/configs/memtest.py ca98021c3f96
tests/configs/o3-timing-mp.py ca98021c3f96
tests/configs/o3-timing.py ca98021c3f96
tests/configs/simple-atomic-mp.py ca98021c3f96
tests/configs/simple-atomic.py ca98021c3f96
tests/configs/simple-timing-mp-ruby.py ca98021c3f96
tests/configs/simple-timing-mp.py ca98021c3f96
tests/configs/simple-timing-ruby.py ca98021c3f96
tests/configs/simple-timing.py ca98021c3f96

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Andreas Hansson
2011-12-23 08:58:46 UTC
Permalink
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http://reviews.m5sim.org/r/943/
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(Updated 2011-12-23 00:58:45.987511)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

This is a complete re-make of the previous patches taking all the
feedback into account.

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py ca98021c3f96
configs/ruby/Ruby.py ca98021c3f96
src/arch/alpha/freebsd/system.cc ca98021c3f96
src/arch/alpha/linux/process.cc ca98021c3f96
src/arch/alpha/linux/system.hh ca98021c3f96
src/arch/alpha/linux/system.cc ca98021c3f96
src/arch/alpha/linux/threadinfo.hh ca98021c3f96
src/arch/alpha/remote_gdb.cc ca98021c3f96
src/arch/alpha/stacktrace.cc ca98021c3f96
src/arch/alpha/system.hh ca98021c3f96
src/arch/alpha/system.cc ca98021c3f96
src/arch/alpha/tru64/process.cc ca98021c3f96
src/arch/alpha/tru64/system.cc ca98021c3f96
src/arch/alpha/utility.cc ca98021c3f96
src/arch/alpha/vtophys.hh ca98021c3f96
src/arch/alpha/vtophys.cc ca98021c3f96
src/arch/arm/linux/process.cc ca98021c3f96
src/arch/arm/linux/system.cc ca98021c3f96
src/arch/arm/process.cc ca98021c3f96
src/arch/arm/stacktrace.cc ca98021c3f96
src/arch/arm/system.hh ca98021c3f96
src/arch/arm/system.cc ca98021c3f96
src/arch/arm/utility.cc ca98021c3f96
src/arch/arm/vtophys.cc ca98021c3f96
src/arch/mips/linux/process.cc ca98021c3f96
src/arch/mips/linux/system.cc ca98021c3f96
src/arch/mips/linux/threadinfo.hh ca98021c3f96
src/arch/mips/stacktrace.cc ca98021c3f96
src/arch/mips/utility.cc ca98021c3f96
src/arch/power/linux/process.cc ca98021c3f96
src/arch/power/process.cc ca98021c3f96
src/arch/sparc/linux/syscalls.cc ca98021c3f96
src/arch/sparc/process.cc ca98021c3f96
src/arch/sparc/solaris/process.cc ca98021c3f96
src/arch/sparc/system.hh ca98021c3f96
src/arch/sparc/system.cc ca98021c3f96
src/arch/sparc/utility.cc ca98021c3f96
src/arch/sparc/vtophys.cc ca98021c3f96
src/arch/x86/bios/intelmp.hh ca98021c3f96
src/arch/x86/bios/intelmp.cc ca98021c3f96
src/arch/x86/bios/smbios.hh ca98021c3f96
src/arch/x86/bios/smbios.cc ca98021c3f96
src/arch/x86/linux/syscalls.cc ca98021c3f96
src/arch/x86/linux/system.cc ca98021c3f96
src/arch/x86/process.cc ca98021c3f96
src/arch/x86/stacktrace.cc ca98021c3f96
src/arch/x86/system.cc ca98021c3f96
src/base/loader/elf_object.hh ca98021c3f96
src/base/loader/elf_object.cc ca98021c3f96
src/base/loader/hex_file.hh ca98021c3f96
src/base/loader/hex_file.cc ca98021c3f96
src/base/loader/object_file.hh ca98021c3f96
src/base/loader/object_file.cc ca98021c3f96
src/base/remote_gdb.cc ca98021c3f96
src/cpu/checker/thread_context.hh ca98021c3f96
src/cpu/inorder/cpu.cc ca98021c3f96
src/cpu/inorder/thread_context.hh ca98021c3f96
src/cpu/inorder/thread_context.cc ca98021c3f96
src/cpu/o3/thread_context.hh ca98021c3f96
src/cpu/o3/thread_context_impl.hh ca98021c3f96
src/cpu/ozone/cpu.hh ca98021c3f96
src/cpu/ozone/cpu_impl.hh ca98021c3f96
src/cpu/simple_thread.hh ca98021c3f96
src/cpu/simple_thread.cc ca98021c3f96
src/cpu/thread_context.hh ca98021c3f96
src/cpu/thread_state.hh ca98021c3f96
src/cpu/thread_state.cc ca98021c3f96
src/dev/simple_disk.cc ca98021c3f96
src/kern/tru64/tru64.hh ca98021c3f96
src/kern/tru64/tru64_events.cc ca98021c3f96
src/mem/SConscript ca98021c3f96
src/mem/bus.cc ca98021c3f96
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh ca98021c3f96
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc ca98021c3f96
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript ca98021c3f96
src/mem/ruby/system/Sequencer.py ca98021c3f96
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh ca98021c3f96
src/mem/translating_port.cc ca98021c3f96
src/mem/vport.hh ca98021c3f96
src/mem/vport.cc ca98021c3f96
src/sim/arguments.hh ca98021c3f96
src/sim/process.hh ca98021c3f96
src/sim/process.cc ca98021c3f96
src/sim/process_impl.hh ca98021c3f96
src/sim/syscall_emul.hh ca98021c3f96
src/sim/syscall_emul.cc ca98021c3f96
src/sim/system.hh ca98021c3f96
src/sim/system.cc ca98021c3f96
src/sim/vptr.hh ca98021c3f96
tests/configs/inorder-timing.py ca98021c3f96
tests/configs/memtest.py ca98021c3f96
tests/configs/o3-timing-mp.py ca98021c3f96
tests/configs/o3-timing.py ca98021c3f96
tests/configs/simple-atomic-mp.py ca98021c3f96
tests/configs/simple-atomic.py ca98021c3f96
tests/configs/simple-timing-mp-ruby.py ca98021c3f96
tests/configs/simple-timing-mp.py ca98021c3f96
tests/configs/simple-timing-ruby.py ca98021c3f96
tests/configs/simple-timing.py ca98021c3f96

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Ali Saidi
2012-01-04 00:25:00 UTC
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Ship it!



src/cpu/simple_thread.cc
<http://reviews.m5sim.org/r/943/#comment2333>

This seems like a bad plan. Probably best to juts leave it around.


- Ali
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2011-12-23 00:58:45)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
This is a complete re-make of the previous patches taking all the
feedback into account.
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py ca98021c3f96
configs/ruby/Ruby.py ca98021c3f96
src/arch/alpha/freebsd/system.cc ca98021c3f96
src/arch/alpha/linux/process.cc ca98021c3f96
src/arch/alpha/linux/system.hh ca98021c3f96
src/arch/alpha/linux/system.cc ca98021c3f96
src/arch/alpha/linux/threadinfo.hh ca98021c3f96
src/arch/alpha/remote_gdb.cc ca98021c3f96
src/arch/alpha/stacktrace.cc ca98021c3f96
src/arch/alpha/system.hh ca98021c3f96
src/arch/alpha/system.cc ca98021c3f96
src/arch/alpha/tru64/process.cc ca98021c3f96
src/arch/alpha/tru64/system.cc ca98021c3f96
src/arch/alpha/utility.cc ca98021c3f96
src/arch/alpha/vtophys.hh ca98021c3f96
src/arch/alpha/vtophys.cc ca98021c3f96
src/arch/arm/linux/process.cc ca98021c3f96
src/arch/arm/linux/system.cc ca98021c3f96
src/arch/arm/process.cc ca98021c3f96
src/arch/arm/stacktrace.cc ca98021c3f96
src/arch/arm/system.hh ca98021c3f96
src/arch/arm/system.cc ca98021c3f96
src/arch/arm/utility.cc ca98021c3f96
src/arch/arm/vtophys.cc ca98021c3f96
src/arch/mips/linux/process.cc ca98021c3f96
src/arch/mips/linux/system.cc ca98021c3f96
src/arch/mips/linux/threadinfo.hh ca98021c3f96
src/arch/mips/stacktrace.cc ca98021c3f96
src/arch/mips/utility.cc ca98021c3f96
src/arch/power/linux/process.cc ca98021c3f96
src/arch/power/process.cc ca98021c3f96
src/arch/sparc/linux/syscalls.cc ca98021c3f96
src/arch/sparc/process.cc ca98021c3f96
src/arch/sparc/solaris/process.cc ca98021c3f96
src/arch/sparc/system.hh ca98021c3f96
src/arch/sparc/system.cc ca98021c3f96
src/arch/sparc/utility.cc ca98021c3f96
src/arch/sparc/vtophys.cc ca98021c3f96
src/arch/x86/bios/intelmp.hh ca98021c3f96
src/arch/x86/bios/intelmp.cc ca98021c3f96
src/arch/x86/bios/smbios.hh ca98021c3f96
src/arch/x86/bios/smbios.cc ca98021c3f96
src/arch/x86/linux/syscalls.cc ca98021c3f96
src/arch/x86/linux/system.cc ca98021c3f96
src/arch/x86/process.cc ca98021c3f96
src/arch/x86/stacktrace.cc ca98021c3f96
src/arch/x86/system.cc ca98021c3f96
src/base/loader/elf_object.hh ca98021c3f96
src/base/loader/elf_object.cc ca98021c3f96
src/base/loader/hex_file.hh ca98021c3f96
src/base/loader/hex_file.cc ca98021c3f96
src/base/loader/object_file.hh ca98021c3f96
src/base/loader/object_file.cc ca98021c3f96
src/base/remote_gdb.cc ca98021c3f96
src/cpu/checker/thread_context.hh ca98021c3f96
src/cpu/inorder/cpu.cc ca98021c3f96
src/cpu/inorder/thread_context.hh ca98021c3f96
src/cpu/inorder/thread_context.cc ca98021c3f96
src/cpu/o3/thread_context.hh ca98021c3f96
src/cpu/o3/thread_context_impl.hh ca98021c3f96
src/cpu/ozone/cpu.hh ca98021c3f96
src/cpu/ozone/cpu_impl.hh ca98021c3f96
src/cpu/simple_thread.hh ca98021c3f96
src/cpu/simple_thread.cc ca98021c3f96
src/cpu/thread_context.hh ca98021c3f96
src/cpu/thread_state.hh ca98021c3f96
src/cpu/thread_state.cc ca98021c3f96
src/dev/simple_disk.cc ca98021c3f96
src/kern/tru64/tru64.hh ca98021c3f96
src/kern/tru64/tru64_events.cc ca98021c3f96
src/mem/SConscript ca98021c3f96
src/mem/bus.cc ca98021c3f96
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh ca98021c3f96
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc ca98021c3f96
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript ca98021c3f96
src/mem/ruby/system/Sequencer.py ca98021c3f96
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh ca98021c3f96
src/mem/translating_port.cc ca98021c3f96
src/mem/vport.hh ca98021c3f96
src/mem/vport.cc ca98021c3f96
src/sim/arguments.hh ca98021c3f96
src/sim/process.hh ca98021c3f96
src/sim/process.cc ca98021c3f96
src/sim/process_impl.hh ca98021c3f96
src/sim/syscall_emul.hh ca98021c3f96
src/sim/syscall_emul.cc ca98021c3f96
src/sim/system.hh ca98021c3f96
src/sim/system.cc ca98021c3f96
src/sim/vptr.hh ca98021c3f96
tests/configs/inorder-timing.py ca98021c3f96
tests/configs/memtest.py ca98021c3f96
tests/configs/o3-timing-mp.py ca98021c3f96
tests/configs/o3-timing.py ca98021c3f96
tests/configs/simple-atomic-mp.py ca98021c3f96
tests/configs/simple-atomic.py ca98021c3f96
tests/configs/simple-timing-mp-ruby.py ca98021c3f96
tests/configs/simple-timing-mp.py ca98021c3f96
tests/configs/simple-timing-ruby.py ca98021c3f96
tests/configs/simple-timing.py ca98021c3f96
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-04 10:32:46 UTC
Permalink
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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/#review1810
-----------------------------------------------------------



src/cpu/simple_thread.cc
<http://reviews.m5sim.org/r/943/#comment2337>

I also believe the SimpleThread should have nothing to do with deleting the port proxies.

I have moved this to the ThreadState destructor since that class is responsible for the creation of the proxies.


- Andreas
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2011-12-23 00:58:45)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
This is a complete re-make of the previous patches taking all the
feedback into account.
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py ca98021c3f96
configs/ruby/Ruby.py ca98021c3f96
src/arch/alpha/freebsd/system.cc ca98021c3f96
src/arch/alpha/linux/process.cc ca98021c3f96
src/arch/alpha/linux/system.hh ca98021c3f96
src/arch/alpha/linux/system.cc ca98021c3f96
src/arch/alpha/linux/threadinfo.hh ca98021c3f96
src/arch/alpha/remote_gdb.cc ca98021c3f96
src/arch/alpha/stacktrace.cc ca98021c3f96
src/arch/alpha/system.hh ca98021c3f96
src/arch/alpha/system.cc ca98021c3f96
src/arch/alpha/tru64/process.cc ca98021c3f96
src/arch/alpha/tru64/system.cc ca98021c3f96
src/arch/alpha/utility.cc ca98021c3f96
src/arch/alpha/vtophys.hh ca98021c3f96
src/arch/alpha/vtophys.cc ca98021c3f96
src/arch/arm/linux/process.cc ca98021c3f96
src/arch/arm/linux/system.cc ca98021c3f96
src/arch/arm/process.cc ca98021c3f96
src/arch/arm/stacktrace.cc ca98021c3f96
src/arch/arm/system.hh ca98021c3f96
src/arch/arm/system.cc ca98021c3f96
src/arch/arm/utility.cc ca98021c3f96
src/arch/arm/vtophys.cc ca98021c3f96
src/arch/mips/linux/process.cc ca98021c3f96
src/arch/mips/linux/system.cc ca98021c3f96
src/arch/mips/linux/threadinfo.hh ca98021c3f96
src/arch/mips/stacktrace.cc ca98021c3f96
src/arch/mips/utility.cc ca98021c3f96
src/arch/power/linux/process.cc ca98021c3f96
src/arch/power/process.cc ca98021c3f96
src/arch/sparc/linux/syscalls.cc ca98021c3f96
src/arch/sparc/process.cc ca98021c3f96
src/arch/sparc/solaris/process.cc ca98021c3f96
src/arch/sparc/system.hh ca98021c3f96
src/arch/sparc/system.cc ca98021c3f96
src/arch/sparc/utility.cc ca98021c3f96
src/arch/sparc/vtophys.cc ca98021c3f96
src/arch/x86/bios/intelmp.hh ca98021c3f96
src/arch/x86/bios/intelmp.cc ca98021c3f96
src/arch/x86/bios/smbios.hh ca98021c3f96
src/arch/x86/bios/smbios.cc ca98021c3f96
src/arch/x86/linux/syscalls.cc ca98021c3f96
src/arch/x86/linux/system.cc ca98021c3f96
src/arch/x86/process.cc ca98021c3f96
src/arch/x86/stacktrace.cc ca98021c3f96
src/arch/x86/system.cc ca98021c3f96
src/base/loader/elf_object.hh ca98021c3f96
src/base/loader/elf_object.cc ca98021c3f96
src/base/loader/hex_file.hh ca98021c3f96
src/base/loader/hex_file.cc ca98021c3f96
src/base/loader/object_file.hh ca98021c3f96
src/base/loader/object_file.cc ca98021c3f96
src/base/remote_gdb.cc ca98021c3f96
src/cpu/checker/thread_context.hh ca98021c3f96
src/cpu/inorder/cpu.cc ca98021c3f96
src/cpu/inorder/thread_context.hh ca98021c3f96
src/cpu/inorder/thread_context.cc ca98021c3f96
src/cpu/o3/thread_context.hh ca98021c3f96
src/cpu/o3/thread_context_impl.hh ca98021c3f96
src/cpu/ozone/cpu.hh ca98021c3f96
src/cpu/ozone/cpu_impl.hh ca98021c3f96
src/cpu/simple_thread.hh ca98021c3f96
src/cpu/simple_thread.cc ca98021c3f96
src/cpu/thread_context.hh ca98021c3f96
src/cpu/thread_state.hh ca98021c3f96
src/cpu/thread_state.cc ca98021c3f96
src/dev/simple_disk.cc ca98021c3f96
src/kern/tru64/tru64.hh ca98021c3f96
src/kern/tru64/tru64_events.cc ca98021c3f96
src/mem/SConscript ca98021c3f96
src/mem/bus.cc ca98021c3f96
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh ca98021c3f96
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc ca98021c3f96
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript ca98021c3f96
src/mem/ruby/system/Sequencer.py ca98021c3f96
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh ca98021c3f96
src/mem/translating_port.cc ca98021c3f96
src/mem/vport.hh ca98021c3f96
src/mem/vport.cc ca98021c3f96
src/sim/arguments.hh ca98021c3f96
src/sim/process.hh ca98021c3f96
src/sim/process.cc ca98021c3f96
src/sim/process_impl.hh ca98021c3f96
src/sim/syscall_emul.hh ca98021c3f96
src/sim/syscall_emul.cc ca98021c3f96
src/sim/system.hh ca98021c3f96
src/sim/system.cc ca98021c3f96
src/sim/vptr.hh ca98021c3f96
tests/configs/inorder-timing.py ca98021c3f96
tests/configs/memtest.py ca98021c3f96
tests/configs/o3-timing-mp.py ca98021c3f96
tests/configs/o3-timing.py ca98021c3f96
tests/configs/simple-atomic-mp.py ca98021c3f96
tests/configs/simple-atomic.py ca98021c3f96
tests/configs/simple-timing-mp-ruby.py ca98021c3f96
tests/configs/simple-timing-mp.py ca98021c3f96
tests/configs/simple-timing-ruby.py ca98021c3f96
tests/configs/simple-timing.py ca98021c3f96
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-04 13:58:06 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-04 05:58:06.864191)


Review request for Default.


Summary (updated)
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py 09b482ee9ae0
configs/ruby/Ruby.py 09b482ee9ae0
src/arch/alpha/freebsd/system.cc 09b482ee9ae0
src/arch/alpha/linux/process.cc 09b482ee9ae0
src/arch/alpha/linux/system.hh 09b482ee9ae0
src/arch/alpha/linux/system.cc 09b482ee9ae0
src/arch/alpha/linux/threadinfo.hh 09b482ee9ae0
src/arch/alpha/remote_gdb.cc 09b482ee9ae0
src/arch/alpha/stacktrace.cc 09b482ee9ae0
src/arch/alpha/system.hh 09b482ee9ae0
src/arch/alpha/system.cc 09b482ee9ae0
src/arch/alpha/tru64/process.cc 09b482ee9ae0
src/arch/alpha/tru64/system.cc 09b482ee9ae0
src/arch/alpha/utility.cc 09b482ee9ae0
src/arch/alpha/vtophys.hh 09b482ee9ae0
src/arch/alpha/vtophys.cc 09b482ee9ae0
src/arch/arm/linux/process.cc 09b482ee9ae0
src/arch/arm/linux/system.cc 09b482ee9ae0
src/arch/arm/process.cc 09b482ee9ae0
src/arch/arm/stacktrace.cc 09b482ee9ae0
src/arch/arm/system.hh 09b482ee9ae0
src/arch/arm/system.cc 09b482ee9ae0
src/arch/arm/utility.cc 09b482ee9ae0
src/arch/arm/vtophys.cc 09b482ee9ae0
src/arch/mips/linux/process.cc 09b482ee9ae0
src/arch/mips/linux/system.cc 09b482ee9ae0
src/arch/mips/linux/threadinfo.hh 09b482ee9ae0
src/arch/mips/stacktrace.cc 09b482ee9ae0
src/arch/mips/utility.cc 09b482ee9ae0
src/arch/power/linux/process.cc 09b482ee9ae0
src/arch/power/process.cc 09b482ee9ae0
src/arch/sparc/linux/syscalls.cc 09b482ee9ae0
src/arch/sparc/process.cc 09b482ee9ae0
src/arch/sparc/solaris/process.cc 09b482ee9ae0
src/arch/sparc/system.hh 09b482ee9ae0
src/arch/sparc/system.cc 09b482ee9ae0
src/arch/sparc/utility.cc 09b482ee9ae0
src/arch/sparc/vtophys.cc 09b482ee9ae0
src/arch/x86/bios/intelmp.hh 09b482ee9ae0
src/arch/x86/bios/intelmp.cc 09b482ee9ae0
src/arch/x86/bios/smbios.hh 09b482ee9ae0
src/arch/x86/bios/smbios.cc 09b482ee9ae0
src/arch/x86/linux/syscalls.cc 09b482ee9ae0
src/arch/x86/linux/system.cc 09b482ee9ae0
src/arch/x86/process.cc 09b482ee9ae0
src/arch/x86/stacktrace.cc 09b482ee9ae0
src/arch/x86/system.cc 09b482ee9ae0
src/base/loader/elf_object.hh 09b482ee9ae0
src/base/loader/elf_object.cc 09b482ee9ae0
src/base/loader/hex_file.hh 09b482ee9ae0
src/base/loader/hex_file.cc 09b482ee9ae0
src/base/loader/object_file.hh 09b482ee9ae0
src/base/loader/object_file.cc 09b482ee9ae0
src/base/remote_gdb.cc 09b482ee9ae0
src/cpu/checker/thread_context.hh 09b482ee9ae0
src/cpu/inorder/cpu.hh 09b482ee9ae0
src/cpu/inorder/cpu.cc 09b482ee9ae0
src/cpu/inorder/resources/cache_unit.hh 09b482ee9ae0
src/cpu/inorder/resources/cache_unit.cc 09b482ee9ae0
src/cpu/inorder/thread_context.hh 09b482ee9ae0
src/cpu/inorder/thread_context.cc 09b482ee9ae0
src/cpu/o3/cpu.hh 09b482ee9ae0
src/cpu/o3/cpu.cc 09b482ee9ae0
src/cpu/o3/lsq.hh 09b482ee9ae0
src/cpu/o3/lsq_impl.hh 09b482ee9ae0
src/cpu/o3/thread_context.hh 09b482ee9ae0
src/cpu/o3/thread_context_impl.hh 09b482ee9ae0
src/cpu/ozone/cpu.hh 09b482ee9ae0
src/cpu/ozone/cpu_impl.hh 09b482ee9ae0
src/cpu/simple/atomic.hh 09b482ee9ae0
src/cpu/simple/atomic.cc 09b482ee9ae0
src/cpu/simple/timing.hh 09b482ee9ae0
src/cpu/simple/timing.cc 09b482ee9ae0
src/cpu/simple_thread.hh 09b482ee9ae0
src/cpu/simple_thread.cc 09b482ee9ae0
src/cpu/thread_context.hh 09b482ee9ae0
src/cpu/thread_state.hh 09b482ee9ae0
src/cpu/thread_state.cc 09b482ee9ae0
src/dev/simple_disk.cc 09b482ee9ae0
src/kern/tru64/tru64.hh 09b482ee9ae0
src/kern/tru64/tru64_events.cc 09b482ee9ae0
src/mem/SConscript 09b482ee9ae0
src/mem/bus.cc 09b482ee9ae0
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 09b482ee9ae0
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 09b482ee9ae0
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 09b482ee9ae0
src/mem/ruby/system/Sequencer.py 09b482ee9ae0
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 09b482ee9ae0
src/mem/translating_port.cc 09b482ee9ae0
src/mem/vport.hh 09b482ee9ae0
src/mem/vport.cc 09b482ee9ae0
src/sim/arguments.hh 09b482ee9ae0
src/sim/process.hh 09b482ee9ae0
src/sim/process.cc 09b482ee9ae0
src/sim/process_impl.hh 09b482ee9ae0
src/sim/syscall_emul.hh 09b482ee9ae0
src/sim/syscall_emul.cc 09b482ee9ae0
src/sim/system.hh 09b482ee9ae0
src/sim/system.cc 09b482ee9ae0
src/sim/vptr.hh 09b482ee9ae0
tests/configs/inorder-timing.py 09b482ee9ae0
tests/configs/memtest.py 09b482ee9ae0
tests/configs/o3-timing-mp.py 09b482ee9ae0
tests/configs/o3-timing.py 09b482ee9ae0
tests/configs/simple-atomic-mp.py 09b482ee9ae0
tests/configs/simple-atomic.py 09b482ee9ae0
tests/configs/simple-timing-mp-ruby.py 09b482ee9ae0
tests/configs/simple-timing-mp.py 09b482ee9ae0
tests/configs/simple-timing-ruby.py 09b482ee9ae0
tests/configs/simple-timing.py 09b482ee9ae0

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Andreas Hansson
2012-01-05 13:19:34 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-05 05:19:34.408510)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py 09b482ee9ae0
configs/ruby/Ruby.py 09b482ee9ae0
src/arch/alpha/freebsd/system.cc 09b482ee9ae0
src/arch/alpha/linux/process.cc 09b482ee9ae0
src/arch/alpha/linux/system.hh 09b482ee9ae0
src/arch/alpha/linux/system.cc 09b482ee9ae0
src/arch/alpha/linux/threadinfo.hh 09b482ee9ae0
src/arch/alpha/remote_gdb.cc 09b482ee9ae0
src/arch/alpha/stacktrace.cc 09b482ee9ae0
src/arch/alpha/system.hh 09b482ee9ae0
src/arch/alpha/system.cc 09b482ee9ae0
src/arch/alpha/tru64/process.cc 09b482ee9ae0
src/arch/alpha/tru64/system.cc 09b482ee9ae0
src/arch/alpha/utility.cc 09b482ee9ae0
src/arch/alpha/vtophys.hh 09b482ee9ae0
src/arch/alpha/vtophys.cc 09b482ee9ae0
src/arch/arm/linux/process.cc 09b482ee9ae0
src/arch/arm/linux/system.cc 09b482ee9ae0
src/arch/arm/process.cc 09b482ee9ae0
src/arch/arm/stacktrace.cc 09b482ee9ae0
src/arch/arm/system.hh 09b482ee9ae0
src/arch/arm/system.cc 09b482ee9ae0
src/arch/arm/utility.cc 09b482ee9ae0
src/arch/arm/vtophys.cc 09b482ee9ae0
src/arch/mips/linux/process.cc 09b482ee9ae0
src/arch/mips/linux/system.cc 09b482ee9ae0
src/arch/mips/linux/threadinfo.hh 09b482ee9ae0
src/arch/mips/stacktrace.cc 09b482ee9ae0
src/arch/mips/utility.cc 09b482ee9ae0
src/arch/power/linux/process.cc 09b482ee9ae0
src/arch/power/process.cc 09b482ee9ae0
src/arch/sparc/linux/syscalls.cc 09b482ee9ae0
src/arch/sparc/process.cc 09b482ee9ae0
src/arch/sparc/solaris/process.cc 09b482ee9ae0
src/arch/sparc/system.hh 09b482ee9ae0
src/arch/sparc/system.cc 09b482ee9ae0
src/arch/sparc/utility.cc 09b482ee9ae0
src/arch/sparc/vtophys.cc 09b482ee9ae0
src/arch/x86/bios/intelmp.hh 09b482ee9ae0
src/arch/x86/bios/intelmp.cc 09b482ee9ae0
src/arch/x86/bios/smbios.hh 09b482ee9ae0
src/arch/x86/bios/smbios.cc 09b482ee9ae0
src/arch/x86/linux/syscalls.cc 09b482ee9ae0
src/arch/x86/linux/system.cc 09b482ee9ae0
src/arch/x86/process.cc 09b482ee9ae0
src/arch/x86/stacktrace.cc 09b482ee9ae0
src/arch/x86/system.cc 09b482ee9ae0
src/base/loader/elf_object.hh 09b482ee9ae0
src/base/loader/elf_object.cc 09b482ee9ae0
src/base/loader/hex_file.hh 09b482ee9ae0
src/base/loader/hex_file.cc 09b482ee9ae0
src/base/loader/object_file.hh 09b482ee9ae0
src/base/loader/object_file.cc 09b482ee9ae0
src/base/remote_gdb.cc 09b482ee9ae0
src/cpu/checker/thread_context.hh 09b482ee9ae0
src/cpu/inorder/cpu.hh 09b482ee9ae0
src/cpu/inorder/cpu.cc 09b482ee9ae0
src/cpu/inorder/resources/cache_unit.hh 09b482ee9ae0
src/cpu/inorder/resources/cache_unit.cc 09b482ee9ae0
src/cpu/inorder/thread_context.hh 09b482ee9ae0
src/cpu/inorder/thread_context.cc 09b482ee9ae0
src/cpu/o3/cpu.hh 09b482ee9ae0
src/cpu/o3/cpu.cc 09b482ee9ae0
src/cpu/o3/lsq.hh 09b482ee9ae0
src/cpu/o3/lsq_impl.hh 09b482ee9ae0
src/cpu/o3/thread_context.hh 09b482ee9ae0
src/cpu/o3/thread_context_impl.hh 09b482ee9ae0
src/cpu/ozone/cpu.hh 09b482ee9ae0
src/cpu/ozone/cpu_impl.hh 09b482ee9ae0
src/cpu/simple/atomic.hh 09b482ee9ae0
src/cpu/simple/atomic.cc 09b482ee9ae0
src/cpu/simple/timing.hh 09b482ee9ae0
src/cpu/simple/timing.cc 09b482ee9ae0
src/cpu/simple_thread.hh 09b482ee9ae0
src/cpu/simple_thread.cc 09b482ee9ae0
src/cpu/thread_context.hh 09b482ee9ae0
src/cpu/thread_state.hh 09b482ee9ae0
src/cpu/thread_state.cc 09b482ee9ae0
src/dev/simple_disk.cc 09b482ee9ae0
src/kern/tru64/tru64.hh 09b482ee9ae0
src/kern/tru64/tru64_events.cc 09b482ee9ae0
src/mem/SConscript 09b482ee9ae0
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 09b482ee9ae0
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 09b482ee9ae0
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 09b482ee9ae0
src/mem/ruby/system/Sequencer.py 09b482ee9ae0
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 09b482ee9ae0
src/mem/translating_port.cc 09b482ee9ae0
src/mem/vport.hh 09b482ee9ae0
src/mem/vport.cc 09b482ee9ae0
src/sim/arguments.hh 09b482ee9ae0
src/sim/process.hh 09b482ee9ae0
src/sim/process.cc 09b482ee9ae0
src/sim/process_impl.hh 09b482ee9ae0
src/sim/syscall_emul.hh 09b482ee9ae0
src/sim/syscall_emul.cc 09b482ee9ae0
src/sim/system.hh 09b482ee9ae0
src/sim/system.cc 09b482ee9ae0
src/sim/vptr.hh 09b482ee9ae0
tests/configs/inorder-timing.py 09b482ee9ae0
tests/configs/memtest.py 09b482ee9ae0
tests/configs/o3-timing-mp.py 09b482ee9ae0
tests/configs/o3-timing.py 09b482ee9ae0
tests/configs/simple-atomic-mp.py 09b482ee9ae0
tests/configs/simple-atomic.py 09b482ee9ae0
tests/configs/simple-timing-mp-ruby.py 09b482ee9ae0
tests/configs/simple-timing-mp.py 09b482ee9ae0
tests/configs/simple-timing-ruby.py 09b482ee9ae0
tests/configs/simple-timing.py 09b482ee9ae0

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Andreas Hansson
2012-01-06 14:10:22 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-06 06:10:22.217839)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py 58885e2e8a88
configs/ruby/Ruby.py 58885e2e8a88
src/arch/alpha/freebsd/system.cc 58885e2e8a88
src/arch/alpha/linux/process.cc 58885e2e8a88
src/arch/alpha/linux/system.hh 58885e2e8a88
src/arch/alpha/linux/system.cc 58885e2e8a88
src/arch/alpha/linux/threadinfo.hh 58885e2e8a88
src/arch/alpha/remote_gdb.cc 58885e2e8a88
src/arch/alpha/stacktrace.cc 58885e2e8a88
src/arch/alpha/system.hh 58885e2e8a88
src/arch/alpha/system.cc 58885e2e8a88
src/arch/alpha/tru64/process.cc 58885e2e8a88
src/arch/alpha/tru64/system.cc 58885e2e8a88
src/arch/alpha/utility.cc 58885e2e8a88
src/arch/alpha/vtophys.hh 58885e2e8a88
src/arch/alpha/vtophys.cc 58885e2e8a88
src/arch/arm/linux/process.cc 58885e2e8a88
src/arch/arm/linux/system.cc 58885e2e8a88
src/arch/arm/process.cc 58885e2e8a88
src/arch/arm/stacktrace.cc 58885e2e8a88
src/arch/arm/system.hh 58885e2e8a88
src/arch/arm/system.cc 58885e2e8a88
src/arch/arm/utility.cc 58885e2e8a88
src/arch/arm/vtophys.cc 58885e2e8a88
src/arch/mips/linux/process.cc 58885e2e8a88
src/arch/mips/linux/system.cc 58885e2e8a88
src/arch/mips/linux/threadinfo.hh 58885e2e8a88
src/arch/mips/stacktrace.cc 58885e2e8a88
src/arch/mips/utility.cc 58885e2e8a88
src/arch/power/linux/process.cc 58885e2e8a88
src/arch/power/process.cc 58885e2e8a88
src/arch/sparc/linux/syscalls.cc 58885e2e8a88
src/arch/sparc/process.cc 58885e2e8a88
src/arch/sparc/solaris/process.cc 58885e2e8a88
src/arch/sparc/system.hh 58885e2e8a88
src/arch/sparc/system.cc 58885e2e8a88
src/arch/sparc/utility.cc 58885e2e8a88
src/arch/sparc/vtophys.cc 58885e2e8a88
src/arch/x86/bios/intelmp.hh 58885e2e8a88
src/arch/x86/bios/intelmp.cc 58885e2e8a88
src/arch/x86/bios/smbios.hh 58885e2e8a88
src/arch/x86/bios/smbios.cc 58885e2e8a88
src/arch/x86/linux/syscalls.cc 58885e2e8a88
src/arch/x86/linux/system.cc 58885e2e8a88
src/arch/x86/process.cc 58885e2e8a88
src/arch/x86/stacktrace.cc 58885e2e8a88
src/arch/x86/system.cc 58885e2e8a88
src/base/loader/elf_object.hh 58885e2e8a88
src/base/loader/elf_object.cc 58885e2e8a88
src/base/loader/hex_file.hh 58885e2e8a88
src/base/loader/hex_file.cc 58885e2e8a88
src/base/loader/object_file.hh 58885e2e8a88
src/base/loader/object_file.cc 58885e2e8a88
src/base/remote_gdb.cc 58885e2e8a88
src/cpu/checker/thread_context.hh 58885e2e8a88
src/cpu/inorder/cpu.hh 58885e2e8a88
src/cpu/inorder/cpu.cc 58885e2e8a88
src/cpu/inorder/resources/cache_unit.hh 58885e2e8a88
src/cpu/inorder/resources/cache_unit.cc 58885e2e8a88
src/cpu/inorder/thread_context.hh 58885e2e8a88
src/cpu/inorder/thread_context.cc 58885e2e8a88
src/cpu/o3/cpu.hh 58885e2e8a88
src/cpu/o3/cpu.cc 58885e2e8a88
src/cpu/o3/lsq.hh 58885e2e8a88
src/cpu/o3/lsq_impl.hh 58885e2e8a88
src/cpu/o3/thread_context.hh 58885e2e8a88
src/cpu/o3/thread_context_impl.hh 58885e2e8a88
src/cpu/ozone/cpu.hh 58885e2e8a88
src/cpu/ozone/cpu_impl.hh 58885e2e8a88
src/cpu/simple/atomic.hh 58885e2e8a88
src/cpu/simple/atomic.cc 58885e2e8a88
src/cpu/simple/timing.hh 58885e2e8a88
src/cpu/simple/timing.cc 58885e2e8a88
src/cpu/simple_thread.hh 58885e2e8a88
src/cpu/simple_thread.cc 58885e2e8a88
src/cpu/thread_context.hh 58885e2e8a88
src/cpu/thread_state.hh 58885e2e8a88
src/cpu/thread_state.cc 58885e2e8a88
src/dev/simple_disk.cc 58885e2e8a88
src/kern/tru64/tru64.hh 58885e2e8a88
src/kern/tru64/tru64_events.cc 58885e2e8a88
src/mem/SConscript 58885e2e8a88
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 58885e2e8a88
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 58885e2e8a88
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 58885e2e8a88
src/mem/ruby/system/Sequencer.py 58885e2e8a88
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 58885e2e8a88
src/mem/translating_port.cc 58885e2e8a88
src/mem/vport.hh 58885e2e8a88
src/mem/vport.cc 58885e2e8a88
src/sim/arguments.hh 58885e2e8a88
src/sim/process.hh 58885e2e8a88
src/sim/process.cc 58885e2e8a88
src/sim/process_impl.hh 58885e2e8a88
src/sim/syscall_emul.hh 58885e2e8a88
src/sim/syscall_emul.cc 58885e2e8a88
src/sim/system.hh 58885e2e8a88
src/sim/system.cc 58885e2e8a88
src/sim/vptr.hh 58885e2e8a88
tests/configs/inorder-timing.py 58885e2e8a88
tests/configs/memtest.py 58885e2e8a88
tests/configs/o3-timing-mp.py 58885e2e8a88
tests/configs/o3-timing.py 58885e2e8a88
tests/configs/simple-atomic-mp.py 58885e2e8a88
tests/configs/simple-atomic.py 58885e2e8a88
tests/configs/simple-timing-mp-ruby.py 58885e2e8a88
tests/configs/simple-timing-mp.py 58885e2e8a88
tests/configs/simple-timing-ruby.py 58885e2e8a88
tests/configs/simple-timing.py 58885e2e8a88

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Andreas Hansson
2012-01-10 17:20:55 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-10 09:20:54.998430)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py a1d5a0e2e970
configs/example/se.py a1d5a0e2e970
configs/ruby/Ruby.py a1d5a0e2e970
src/arch/alpha/freebsd/system.cc a1d5a0e2e970
src/arch/alpha/linux/process.cc a1d5a0e2e970
src/arch/alpha/linux/system.hh a1d5a0e2e970
src/arch/alpha/linux/system.cc a1d5a0e2e970
src/arch/alpha/linux/threadinfo.hh a1d5a0e2e970
src/arch/alpha/remote_gdb.cc a1d5a0e2e970
src/arch/alpha/stacktrace.cc a1d5a0e2e970
src/arch/alpha/system.hh a1d5a0e2e970
src/arch/alpha/system.cc a1d5a0e2e970
src/arch/alpha/tru64/process.cc a1d5a0e2e970
src/arch/alpha/tru64/system.cc a1d5a0e2e970
src/arch/alpha/utility.cc a1d5a0e2e970
src/arch/alpha/vtophys.hh a1d5a0e2e970
src/arch/alpha/vtophys.cc a1d5a0e2e970
src/arch/arm/linux/process.cc a1d5a0e2e970
src/arch/arm/linux/system.cc a1d5a0e2e970
src/arch/arm/process.cc a1d5a0e2e970
src/arch/arm/stacktrace.cc a1d5a0e2e970
src/arch/arm/system.hh a1d5a0e2e970
src/arch/arm/system.cc a1d5a0e2e970
src/arch/arm/utility.cc a1d5a0e2e970
src/arch/arm/vtophys.cc a1d5a0e2e970
src/arch/mips/linux/process.cc a1d5a0e2e970
src/arch/mips/linux/system.cc a1d5a0e2e970
src/arch/mips/linux/threadinfo.hh a1d5a0e2e970
src/arch/mips/stacktrace.cc a1d5a0e2e970
src/arch/mips/utility.cc a1d5a0e2e970
src/arch/power/linux/process.cc a1d5a0e2e970
src/arch/power/process.cc a1d5a0e2e970
src/arch/sparc/linux/syscalls.cc a1d5a0e2e970
src/arch/sparc/process.cc a1d5a0e2e970
src/arch/sparc/solaris/process.cc a1d5a0e2e970
src/arch/sparc/system.hh a1d5a0e2e970
src/arch/sparc/system.cc a1d5a0e2e970
src/arch/sparc/utility.cc a1d5a0e2e970
src/arch/sparc/vtophys.cc a1d5a0e2e970
src/arch/x86/bios/intelmp.hh a1d5a0e2e970
src/arch/x86/bios/intelmp.cc a1d5a0e2e970
src/arch/x86/bios/smbios.hh a1d5a0e2e970
src/arch/x86/bios/smbios.cc a1d5a0e2e970
src/arch/x86/linux/syscalls.cc a1d5a0e2e970
src/arch/x86/linux/system.cc a1d5a0e2e970
src/arch/x86/process.cc a1d5a0e2e970
src/arch/x86/stacktrace.cc a1d5a0e2e970
src/arch/x86/system.cc a1d5a0e2e970
src/base/loader/elf_object.hh a1d5a0e2e970
src/base/loader/elf_object.cc a1d5a0e2e970
src/base/loader/hex_file.hh a1d5a0e2e970
src/base/loader/hex_file.cc a1d5a0e2e970
src/base/loader/object_file.hh a1d5a0e2e970
src/base/loader/object_file.cc a1d5a0e2e970
src/base/remote_gdb.cc a1d5a0e2e970
src/cpu/checker/thread_context.hh a1d5a0e2e970
src/cpu/inorder/cpu.hh a1d5a0e2e970
src/cpu/inorder/cpu.cc a1d5a0e2e970
src/cpu/inorder/resources/cache_unit.hh a1d5a0e2e970
src/cpu/inorder/resources/cache_unit.cc a1d5a0e2e970
src/cpu/inorder/thread_context.hh a1d5a0e2e970
src/cpu/inorder/thread_context.cc a1d5a0e2e970
src/cpu/o3/cpu.hh a1d5a0e2e970
src/cpu/o3/cpu.cc a1d5a0e2e970
src/cpu/o3/lsq.hh a1d5a0e2e970
src/cpu/o3/lsq_impl.hh a1d5a0e2e970
src/cpu/o3/thread_context.hh a1d5a0e2e970
src/cpu/o3/thread_context_impl.hh a1d5a0e2e970
src/cpu/ozone/cpu.hh a1d5a0e2e970
src/cpu/ozone/cpu_impl.hh a1d5a0e2e970
src/cpu/simple/atomic.hh a1d5a0e2e970
src/cpu/simple/atomic.cc a1d5a0e2e970
src/cpu/simple/timing.hh a1d5a0e2e970
src/cpu/simple/timing.cc a1d5a0e2e970
src/cpu/simple_thread.hh a1d5a0e2e970
src/cpu/simple_thread.cc a1d5a0e2e970
src/cpu/thread_context.hh a1d5a0e2e970
src/cpu/thread_state.hh a1d5a0e2e970
src/cpu/thread_state.cc a1d5a0e2e970
src/dev/simple_disk.cc a1d5a0e2e970
src/kern/tru64/tru64.hh a1d5a0e2e970
src/kern/tru64/tru64_events.cc a1d5a0e2e970
src/mem/SConscript a1d5a0e2e970
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh a1d5a0e2e970
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc a1d5a0e2e970
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript a1d5a0e2e970
src/mem/ruby/system/Sequencer.py a1d5a0e2e970
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh a1d5a0e2e970
src/mem/translating_port.cc a1d5a0e2e970
src/mem/vport.hh a1d5a0e2e970
src/mem/vport.cc a1d5a0e2e970
src/sim/arguments.hh a1d5a0e2e970
src/sim/process.hh a1d5a0e2e970
src/sim/process.cc a1d5a0e2e970
src/sim/process_impl.hh a1d5a0e2e970
src/sim/syscall_emul.hh a1d5a0e2e970
src/sim/syscall_emul.cc a1d5a0e2e970
src/sim/system.hh a1d5a0e2e970
src/sim/system.cc a1d5a0e2e970
src/sim/vptr.hh a1d5a0e2e970
tests/configs/inorder-timing.py a1d5a0e2e970
tests/configs/memtest.py a1d5a0e2e970
tests/configs/o3-timing-mp.py a1d5a0e2e970
tests/configs/o3-timing.py a1d5a0e2e970
tests/configs/simple-atomic-mp.py a1d5a0e2e970
tests/configs/simple-atomic.py a1d5a0e2e970
tests/configs/simple-timing-mp-ruby.py a1d5a0e2e970
tests/configs/simple-timing-mp.py a1d5a0e2e970
tests/configs/simple-timing-ruby.py a1d5a0e2e970
tests/configs/simple-timing.py a1d5a0e2e970

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Andreas Hansson
2012-01-11 11:29:50 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-11 03:29:50.119011)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py 508bbec99e58
configs/example/se.py 508bbec99e58
configs/ruby/Ruby.py 508bbec99e58
src/arch/alpha/freebsd/system.cc 508bbec99e58
src/arch/alpha/linux/process.cc 508bbec99e58
src/arch/alpha/linux/system.hh 508bbec99e58
src/arch/alpha/linux/system.cc 508bbec99e58
src/arch/alpha/linux/threadinfo.hh 508bbec99e58
src/arch/alpha/remote_gdb.cc 508bbec99e58
src/arch/alpha/stacktrace.cc 508bbec99e58
src/arch/alpha/system.hh 508bbec99e58
src/arch/alpha/system.cc 508bbec99e58
src/arch/alpha/tru64/process.cc 508bbec99e58
src/arch/alpha/tru64/system.cc 508bbec99e58
src/arch/alpha/utility.cc 508bbec99e58
src/arch/alpha/vtophys.hh 508bbec99e58
src/arch/alpha/vtophys.cc 508bbec99e58
src/arch/arm/linux/process.cc 508bbec99e58
src/arch/arm/linux/system.cc 508bbec99e58
src/arch/arm/process.cc 508bbec99e58
src/arch/arm/stacktrace.cc 508bbec99e58
src/arch/arm/system.hh 508bbec99e58
src/arch/arm/system.cc 508bbec99e58
src/arch/arm/utility.cc 508bbec99e58
src/arch/arm/vtophys.cc 508bbec99e58
src/arch/mips/linux/process.cc 508bbec99e58
src/arch/mips/linux/system.cc 508bbec99e58
src/arch/mips/linux/threadinfo.hh 508bbec99e58
src/arch/mips/stacktrace.cc 508bbec99e58
src/arch/mips/utility.cc 508bbec99e58
src/arch/power/linux/process.cc 508bbec99e58
src/arch/power/process.cc 508bbec99e58
src/arch/sparc/linux/syscalls.cc 508bbec99e58
src/arch/sparc/process.cc 508bbec99e58
src/arch/sparc/solaris/process.cc 508bbec99e58
src/arch/sparc/system.hh 508bbec99e58
src/arch/sparc/system.cc 508bbec99e58
src/arch/sparc/utility.cc 508bbec99e58
src/arch/sparc/vtophys.cc 508bbec99e58
src/arch/x86/bios/intelmp.hh 508bbec99e58
src/arch/x86/bios/intelmp.cc 508bbec99e58
src/arch/x86/bios/smbios.hh 508bbec99e58
src/arch/x86/bios/smbios.cc 508bbec99e58
src/arch/x86/linux/syscalls.cc 508bbec99e58
src/arch/x86/linux/system.cc 508bbec99e58
src/arch/x86/process.cc 508bbec99e58
src/arch/x86/stacktrace.cc 508bbec99e58
src/arch/x86/system.cc 508bbec99e58
src/base/loader/elf_object.hh 508bbec99e58
src/base/loader/elf_object.cc 508bbec99e58
src/base/loader/hex_file.hh 508bbec99e58
src/base/loader/hex_file.cc 508bbec99e58
src/base/loader/object_file.hh 508bbec99e58
src/base/loader/object_file.cc 508bbec99e58
src/base/remote_gdb.cc 508bbec99e58
src/cpu/checker/thread_context.hh 508bbec99e58
src/cpu/inorder/cpu.hh 508bbec99e58
src/cpu/inorder/cpu.cc 508bbec99e58
src/cpu/inorder/resources/cache_unit.hh 508bbec99e58
src/cpu/inorder/resources/cache_unit.cc 508bbec99e58
src/cpu/inorder/thread_context.hh 508bbec99e58
src/cpu/inorder/thread_context.cc 508bbec99e58
src/cpu/o3/cpu.hh 508bbec99e58
src/cpu/o3/cpu.cc 508bbec99e58
src/cpu/o3/lsq.hh 508bbec99e58
src/cpu/o3/lsq_impl.hh 508bbec99e58
src/cpu/o3/thread_context.hh 508bbec99e58
src/cpu/o3/thread_context_impl.hh 508bbec99e58
src/cpu/ozone/cpu.hh 508bbec99e58
src/cpu/ozone/cpu_impl.hh 508bbec99e58
src/cpu/simple/atomic.hh 508bbec99e58
src/cpu/simple/atomic.cc 508bbec99e58
src/cpu/simple/timing.hh 508bbec99e58
src/cpu/simple/timing.cc 508bbec99e58
src/cpu/simple_thread.hh 508bbec99e58
src/cpu/simple_thread.cc 508bbec99e58
src/cpu/thread_context.hh 508bbec99e58
src/cpu/thread_state.hh 508bbec99e58
src/cpu/thread_state.cc 508bbec99e58
src/dev/simple_disk.cc 508bbec99e58
src/kern/tru64/tru64.hh 508bbec99e58
src/kern/tru64/tru64_events.cc 508bbec99e58
src/mem/SConscript 508bbec99e58
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 508bbec99e58
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 508bbec99e58
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 508bbec99e58
src/mem/ruby/system/Sequencer.py 508bbec99e58
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 508bbec99e58
src/mem/translating_port.cc 508bbec99e58
src/mem/vport.hh 508bbec99e58
src/mem/vport.cc 508bbec99e58
src/sim/arguments.hh 508bbec99e58
src/sim/process.hh 508bbec99e58
src/sim/process.cc 508bbec99e58
src/sim/process_impl.hh 508bbec99e58
src/sim/syscall_emul.hh 508bbec99e58
src/sim/syscall_emul.cc 508bbec99e58
src/sim/system.hh 508bbec99e58
src/sim/system.cc 508bbec99e58
src/sim/vptr.hh 508bbec99e58
tests/configs/inorder-timing.py 508bbec99e58
tests/configs/memtest.py 508bbec99e58
tests/configs/o3-timing-mp.py 508bbec99e58
tests/configs/o3-timing.py 508bbec99e58
tests/configs/simple-atomic-mp.py 508bbec99e58
tests/configs/simple-atomic.py 508bbec99e58
tests/configs/simple-timing-mp-ruby.py 508bbec99e58
tests/configs/simple-timing-mp.py 508bbec99e58
tests/configs/simple-timing-ruby.py 508bbec99e58
tests/configs/simple-timing.py 508bbec99e58

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Steve Reinhardt
2012-01-12 04:35:11 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/#review1921
-----------------------------------------------------------


Looks pretty good... several comments below (some minor, a couple more significant ones), and there's also the pointer declaration style issue to iron out, but it looks pretty close.

I think this is my last patch to review of your series, Andreas. I think there were only a couple (including this one) I didn't mark as "ship it"... those are the only ones I care to see again before you commit.

Thanks for all your hard work!


src/mem/fs_translating_port_proxy.hh
<http://reviews.m5sim.org/r/943/#comment2420>

Typo in "boundaries" in this and the next comment. Unless it's some variant British spelling I'm unaware of :).



src/mem/fs_translating_port_proxy.hh
<http://reviews.m5sim.org/r/943/#comment2426>

Are these read/write/readGtoH/writeHtoG methods used anywhere? I didn't see them on VirtualPort and I don't recall any uses elsewhere in this patch.

I'm concerned because we could get into cases where these are unaligned and cross page boundaries, and the current code doesn't deal with that.



src/mem/fs_translating_port_proxy.hh
<http://reviews.m5sim.org/r/943/#comment2421>

If you add a private inline method like:

Addr
translate(Addr va)
{
if (_tc == NULL) {
return TheISA::vtophys(address);
} else {
return TheISA::vtophys(_tc, address);
}
}

then you could turn all of these functions into one-liners, and simplify a lot of the functions in the .cc file too.




src/mem/fs_translating_port_proxy.cc
<http://reviews.m5sim.org/r/943/#comment2423>

I'd really like to see these done in mercurial as file renames rather than a combination of new and deleted files... e.g., this should be a rename of vport.cc not a new file. Similarly for translating_port.{cc,hh} -> se_translating_proxy.{cc,hh}



src/mem/fs_translating_port_proxy.cc
<http://reviews.m5sim.org/r/943/#comment2422>

need space after the comma here (and several similar places)



src/mem/fs_translating_port_proxy.cc
<http://reviews.m5sim.org/r/943/#comment2424>

This comment is totally outside the scope of this patch, but seeing this code again reminds me how much it annoys me, mainly because these are global functions that start with a capital (predating, but way in violation of, the style guide). It seems to me that these might be best as methods on ThreadContext, and then they could eventually be usable in SE mode too.



src/mem/port_proxy.cc
<http://reviews.m5sim.org/r/943/#comment2425>

I'd be fine with inlining these into port_proxy.hh and getting rid of this file... seems like overkill to have a separate .cc, and they're short enough it's probably worth inlining them anyway.


- Steve
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-11 03:29:50)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 508bbec99e58
configs/example/se.py 508bbec99e58
configs/ruby/Ruby.py 508bbec99e58
src/arch/alpha/freebsd/system.cc 508bbec99e58
src/arch/alpha/linux/process.cc 508bbec99e58
src/arch/alpha/linux/system.hh 508bbec99e58
src/arch/alpha/linux/system.cc 508bbec99e58
src/arch/alpha/linux/threadinfo.hh 508bbec99e58
src/arch/alpha/remote_gdb.cc 508bbec99e58
src/arch/alpha/stacktrace.cc 508bbec99e58
src/arch/alpha/system.hh 508bbec99e58
src/arch/alpha/system.cc 508bbec99e58
src/arch/alpha/tru64/process.cc 508bbec99e58
src/arch/alpha/tru64/system.cc 508bbec99e58
src/arch/alpha/utility.cc 508bbec99e58
src/arch/alpha/vtophys.hh 508bbec99e58
src/arch/alpha/vtophys.cc 508bbec99e58
src/arch/arm/linux/process.cc 508bbec99e58
src/arch/arm/linux/system.cc 508bbec99e58
src/arch/arm/process.cc 508bbec99e58
src/arch/arm/stacktrace.cc 508bbec99e58
src/arch/arm/system.hh 508bbec99e58
src/arch/arm/system.cc 508bbec99e58
src/arch/arm/utility.cc 508bbec99e58
src/arch/arm/vtophys.cc 508bbec99e58
src/arch/mips/linux/process.cc 508bbec99e58
src/arch/mips/linux/system.cc 508bbec99e58
src/arch/mips/linux/threadinfo.hh 508bbec99e58
src/arch/mips/stacktrace.cc 508bbec99e58
src/arch/mips/utility.cc 508bbec99e58
src/arch/power/linux/process.cc 508bbec99e58
src/arch/power/process.cc 508bbec99e58
src/arch/sparc/linux/syscalls.cc 508bbec99e58
src/arch/sparc/process.cc 508bbec99e58
src/arch/sparc/solaris/process.cc 508bbec99e58
src/arch/sparc/system.hh 508bbec99e58
src/arch/sparc/system.cc 508bbec99e58
src/arch/sparc/utility.cc 508bbec99e58
src/arch/sparc/vtophys.cc 508bbec99e58
src/arch/x86/bios/intelmp.hh 508bbec99e58
src/arch/x86/bios/intelmp.cc 508bbec99e58
src/arch/x86/bios/smbios.hh 508bbec99e58
src/arch/x86/bios/smbios.cc 508bbec99e58
src/arch/x86/linux/syscalls.cc 508bbec99e58
src/arch/x86/linux/system.cc 508bbec99e58
src/arch/x86/process.cc 508bbec99e58
src/arch/x86/stacktrace.cc 508bbec99e58
src/arch/x86/system.cc 508bbec99e58
src/base/loader/elf_object.hh 508bbec99e58
src/base/loader/elf_object.cc 508bbec99e58
src/base/loader/hex_file.hh 508bbec99e58
src/base/loader/hex_file.cc 508bbec99e58
src/base/loader/object_file.hh 508bbec99e58
src/base/loader/object_file.cc 508bbec99e58
src/base/remote_gdb.cc 508bbec99e58
src/cpu/checker/thread_context.hh 508bbec99e58
src/cpu/inorder/cpu.hh 508bbec99e58
src/cpu/inorder/cpu.cc 508bbec99e58
src/cpu/inorder/resources/cache_unit.hh 508bbec99e58
src/cpu/inorder/resources/cache_unit.cc 508bbec99e58
src/cpu/inorder/thread_context.hh 508bbec99e58
src/cpu/inorder/thread_context.cc 508bbec99e58
src/cpu/o3/cpu.hh 508bbec99e58
src/cpu/o3/cpu.cc 508bbec99e58
src/cpu/o3/lsq.hh 508bbec99e58
src/cpu/o3/lsq_impl.hh 508bbec99e58
src/cpu/o3/thread_context.hh 508bbec99e58
src/cpu/o3/thread_context_impl.hh 508bbec99e58
src/cpu/ozone/cpu.hh 508bbec99e58
src/cpu/ozone/cpu_impl.hh 508bbec99e58
src/cpu/simple/atomic.hh 508bbec99e58
src/cpu/simple/atomic.cc 508bbec99e58
src/cpu/simple/timing.hh 508bbec99e58
src/cpu/simple/timing.cc 508bbec99e58
src/cpu/simple_thread.hh 508bbec99e58
src/cpu/simple_thread.cc 508bbec99e58
src/cpu/thread_context.hh 508bbec99e58
src/cpu/thread_state.hh 508bbec99e58
src/cpu/thread_state.cc 508bbec99e58
src/dev/simple_disk.cc 508bbec99e58
src/kern/tru64/tru64.hh 508bbec99e58
src/kern/tru64/tru64_events.cc 508bbec99e58
src/mem/SConscript 508bbec99e58
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 508bbec99e58
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 508bbec99e58
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 508bbec99e58
src/mem/ruby/system/Sequencer.py 508bbec99e58
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 508bbec99e58
src/mem/translating_port.cc 508bbec99e58
src/mem/vport.hh 508bbec99e58
src/mem/vport.cc 508bbec99e58
src/sim/arguments.hh 508bbec99e58
src/sim/process.hh 508bbec99e58
src/sim/process.cc 508bbec99e58
src/sim/process_impl.hh 508bbec99e58
src/sim/syscall_emul.hh 508bbec99e58
src/sim/syscall_emul.cc 508bbec99e58
src/sim/system.hh 508bbec99e58
src/sim/system.cc 508bbec99e58
src/sim/vptr.hh 508bbec99e58
tests/configs/inorder-timing.py 508bbec99e58
tests/configs/memtest.py 508bbec99e58
tests/configs/o3-timing-mp.py 508bbec99e58
tests/configs/o3-timing.py 508bbec99e58
tests/configs/simple-atomic-mp.py 508bbec99e58
tests/configs/simple-atomic.py 508bbec99e58
tests/configs/simple-timing-mp-ruby.py 508bbec99e58
tests/configs/simple-timing-mp.py 508bbec99e58
tests/configs/simple-timing-ruby.py 508bbec99e58
tests/configs/simple-timing.py 508bbec99e58
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-12 08:38:25 UTC
Permalink
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.hh, line 86
<http://reviews.m5sim.org/r/943/diff/7/?file=20692#file20692line86>
Typo in "boundaries" in this and the next comment. Unless it's some variant British spelling I'm unaware of :).
Fixed :)
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.hh, line 102
<http://reviews.m5sim.org/r/943/diff/7/?file=20692#file20692line102>
Are these read/write/readGtoH/writeHtoG methods used anywhere? I didn't see them on VirtualPort and I don't recall any uses elsewhere in this patch.
I'm concerned because we could get into cases where these are unaligned and cross page boundaries, and the current code doesn't deal with that.
I haven't tidied up the code at all, but I can of course do so. I tried to keep the changes to a minimum and only do the file rename and the absolutely necessary edits. Obviously that doesn't seem to have worked very well.
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.hh, line 129
<http://reviews.m5sim.org/r/943/diff/7/?file=20692#file20692line129>
Addr
translate(Addr va)
{
if (_tc == NULL) {
return TheISA::vtophys(address);
} else {
return TheISA::vtophys(_tc, address);
}
}
then you could turn all of these functions into one-liners, and simplify a lot of the functions in the .cc file too.
Once again, I haven't tidied up the code at all to minimise the changes. I can perform this change, but would rather make it a second "cleanup" patch.
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.cc, line 1
<http://reviews.m5sim.org/r/943/diff/7/?file=20693#file20693line1>
I'd really like to see these done in mercurial as file renames rather than a combination of new and deleted files... e.g., this should be a rename of vport.cc not a new file. Similarly for translating_port.{cc,hh} -> se_translating_proxy.{cc,hh}
I did do them as file renames, just as you have suggested. I did not do that for the first iteration of these changes (as I am sure you remember), and the very first step of the second iteration was exactly the renames you suggest. I don't know why the review board does not like this or gets it wrong.
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.cc, line 78
<http://reviews.m5sim.org/r/943/diff/7/?file=20693#file20693line78>
need space after the comma here (and several similar places)
Once again, I've tried to not change anything unless I have to, but would be very happy to do so. I'm itching to make things look decent, and really had to try hard not to fix it.
Post by Andreas Hansson
src/mem/fs_translating_port_proxy.cc, line 121
<http://reviews.m5sim.org/r/943/diff/7/?file=20693#file20693line121>
This comment is totally outside the scope of this patch, but seeing this code again reminds me how much it annoys me, mainly because these are global functions that start with a capital (predating, but way in violation of, the style guide). It seems to me that these might be best as methods on ThreadContext, and then they could eventually be usable in SE mode too.
I think that is a brilliant suggestion and would be keen to clean it up as well. I would imagine we should wait until Gabe is done with the SE/FS merge.
Post by Andreas Hansson
src/mem/port_proxy.cc, line 40
<http://reviews.m5sim.org/r/943/diff/7/?file=20696#file20696line40>
I'd be fine with inlining these into port_proxy.hh and getting rid of this file... seems like overkill to have a separate .cc, and they're short enough it's probably worth inlining them anyway.
Will do so!


- Andreas


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/#review1921
-----------------------------------------------------------
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-11 03:29:50)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 508bbec99e58
configs/example/se.py 508bbec99e58
configs/ruby/Ruby.py 508bbec99e58
src/arch/alpha/freebsd/system.cc 508bbec99e58
src/arch/alpha/linux/process.cc 508bbec99e58
src/arch/alpha/linux/system.hh 508bbec99e58
src/arch/alpha/linux/system.cc 508bbec99e58
src/arch/alpha/linux/threadinfo.hh 508bbec99e58
src/arch/alpha/remote_gdb.cc 508bbec99e58
src/arch/alpha/stacktrace.cc 508bbec99e58
src/arch/alpha/system.hh 508bbec99e58
src/arch/alpha/system.cc 508bbec99e58
src/arch/alpha/tru64/process.cc 508bbec99e58
src/arch/alpha/tru64/system.cc 508bbec99e58
src/arch/alpha/utility.cc 508bbec99e58
src/arch/alpha/vtophys.hh 508bbec99e58
src/arch/alpha/vtophys.cc 508bbec99e58
src/arch/arm/linux/process.cc 508bbec99e58
src/arch/arm/linux/system.cc 508bbec99e58
src/arch/arm/process.cc 508bbec99e58
src/arch/arm/stacktrace.cc 508bbec99e58
src/arch/arm/system.hh 508bbec99e58
src/arch/arm/system.cc 508bbec99e58
src/arch/arm/utility.cc 508bbec99e58
src/arch/arm/vtophys.cc 508bbec99e58
src/arch/mips/linux/process.cc 508bbec99e58
src/arch/mips/linux/system.cc 508bbec99e58
src/arch/mips/linux/threadinfo.hh 508bbec99e58
src/arch/mips/stacktrace.cc 508bbec99e58
src/arch/mips/utility.cc 508bbec99e58
src/arch/power/linux/process.cc 508bbec99e58
src/arch/power/process.cc 508bbec99e58
src/arch/sparc/linux/syscalls.cc 508bbec99e58
src/arch/sparc/process.cc 508bbec99e58
src/arch/sparc/solaris/process.cc 508bbec99e58
src/arch/sparc/system.hh 508bbec99e58
src/arch/sparc/system.cc 508bbec99e58
src/arch/sparc/utility.cc 508bbec99e58
src/arch/sparc/vtophys.cc 508bbec99e58
src/arch/x86/bios/intelmp.hh 508bbec99e58
src/arch/x86/bios/intelmp.cc 508bbec99e58
src/arch/x86/bios/smbios.hh 508bbec99e58
src/arch/x86/bios/smbios.cc 508bbec99e58
src/arch/x86/linux/syscalls.cc 508bbec99e58
src/arch/x86/linux/system.cc 508bbec99e58
src/arch/x86/process.cc 508bbec99e58
src/arch/x86/stacktrace.cc 508bbec99e58
src/arch/x86/system.cc 508bbec99e58
src/base/loader/elf_object.hh 508bbec99e58
src/base/loader/elf_object.cc 508bbec99e58
src/base/loader/hex_file.hh 508bbec99e58
src/base/loader/hex_file.cc 508bbec99e58
src/base/loader/object_file.hh 508bbec99e58
src/base/loader/object_file.cc 508bbec99e58
src/base/remote_gdb.cc 508bbec99e58
src/cpu/checker/thread_context.hh 508bbec99e58
src/cpu/inorder/cpu.hh 508bbec99e58
src/cpu/inorder/cpu.cc 508bbec99e58
src/cpu/inorder/resources/cache_unit.hh 508bbec99e58
src/cpu/inorder/resources/cache_unit.cc 508bbec99e58
src/cpu/inorder/thread_context.hh 508bbec99e58
src/cpu/inorder/thread_context.cc 508bbec99e58
src/cpu/o3/cpu.hh 508bbec99e58
src/cpu/o3/cpu.cc 508bbec99e58
src/cpu/o3/lsq.hh 508bbec99e58
src/cpu/o3/lsq_impl.hh 508bbec99e58
src/cpu/o3/thread_context.hh 508bbec99e58
src/cpu/o3/thread_context_impl.hh 508bbec99e58
src/cpu/ozone/cpu.hh 508bbec99e58
src/cpu/ozone/cpu_impl.hh 508bbec99e58
src/cpu/simple/atomic.hh 508bbec99e58
src/cpu/simple/atomic.cc 508bbec99e58
src/cpu/simple/timing.hh 508bbec99e58
src/cpu/simple/timing.cc 508bbec99e58
src/cpu/simple_thread.hh 508bbec99e58
src/cpu/simple_thread.cc 508bbec99e58
src/cpu/thread_context.hh 508bbec99e58
src/cpu/thread_state.hh 508bbec99e58
src/cpu/thread_state.cc 508bbec99e58
src/dev/simple_disk.cc 508bbec99e58
src/kern/tru64/tru64.hh 508bbec99e58
src/kern/tru64/tru64_events.cc 508bbec99e58
src/mem/SConscript 508bbec99e58
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 508bbec99e58
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 508bbec99e58
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 508bbec99e58
src/mem/ruby/system/Sequencer.py 508bbec99e58
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 508bbec99e58
src/mem/translating_port.cc 508bbec99e58
src/mem/vport.hh 508bbec99e58
src/mem/vport.cc 508bbec99e58
src/sim/arguments.hh 508bbec99e58
src/sim/process.hh 508bbec99e58
src/sim/process.cc 508bbec99e58
src/sim/process_impl.hh 508bbec99e58
src/sim/syscall_emul.hh 508bbec99e58
src/sim/syscall_emul.cc 508bbec99e58
src/sim/system.hh 508bbec99e58
src/sim/system.cc 508bbec99e58
src/sim/vptr.hh 508bbec99e58
tests/configs/inorder-timing.py 508bbec99e58
tests/configs/memtest.py 508bbec99e58
tests/configs/o3-timing-mp.py 508bbec99e58
tests/configs/o3-timing.py 508bbec99e58
tests/configs/simple-atomic-mp.py 508bbec99e58
tests/configs/simple-atomic.py 508bbec99e58
tests/configs/simple-timing-mp-ruby.py 508bbec99e58
tests/configs/simple-timing-mp.py 508bbec99e58
tests/configs/simple-timing-ruby.py 508bbec99e58
tests/configs/simple-timing.py 508bbec99e58
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-12 08:43:41 UTC
Permalink
Post by Andreas Hansson
Post by Steve Reinhardt
Looks pretty good... several comments below (some minor, a couple more significant ones), and there's also the pointer declaration style issue to iron out, but it looks pretty close.
I think this is my last patch to review of your series, Andreas. I think there were only a couple (including this one) I didn't mark as "ship it"... those are the only ones I care to see again before you commit.
Thanks for all your hard work!
Thanks for the review.

Here are a few lines from the patch file, and I have no idea why the board does not like the rename:

diff --git a/src/mem/vport.cc b/src/mem/fs_translating_port_proxy.cc
rename from src/mem/vport.cc
rename to src/mem/fs_translating_port_proxy.cc
--- a/src/mem/vport.cc
+++ b/src/mem/fs_translating_port_proxy.cc


- Andreas


-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/#review1921
-----------------------------------------------------------
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-11 03:29:50)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 508bbec99e58
configs/example/se.py 508bbec99e58
configs/ruby/Ruby.py 508bbec99e58
src/arch/alpha/freebsd/system.cc 508bbec99e58
src/arch/alpha/linux/process.cc 508bbec99e58
src/arch/alpha/linux/system.hh 508bbec99e58
src/arch/alpha/linux/system.cc 508bbec99e58
src/arch/alpha/linux/threadinfo.hh 508bbec99e58
src/arch/alpha/remote_gdb.cc 508bbec99e58
src/arch/alpha/stacktrace.cc 508bbec99e58
src/arch/alpha/system.hh 508bbec99e58
src/arch/alpha/system.cc 508bbec99e58
src/arch/alpha/tru64/process.cc 508bbec99e58
src/arch/alpha/tru64/system.cc 508bbec99e58
src/arch/alpha/utility.cc 508bbec99e58
src/arch/alpha/vtophys.hh 508bbec99e58
src/arch/alpha/vtophys.cc 508bbec99e58
src/arch/arm/linux/process.cc 508bbec99e58
src/arch/arm/linux/system.cc 508bbec99e58
src/arch/arm/process.cc 508bbec99e58
src/arch/arm/stacktrace.cc 508bbec99e58
src/arch/arm/system.hh 508bbec99e58
src/arch/arm/system.cc 508bbec99e58
src/arch/arm/utility.cc 508bbec99e58
src/arch/arm/vtophys.cc 508bbec99e58
src/arch/mips/linux/process.cc 508bbec99e58
src/arch/mips/linux/system.cc 508bbec99e58
src/arch/mips/linux/threadinfo.hh 508bbec99e58
src/arch/mips/stacktrace.cc 508bbec99e58
src/arch/mips/utility.cc 508bbec99e58
src/arch/power/linux/process.cc 508bbec99e58
src/arch/power/process.cc 508bbec99e58
src/arch/sparc/linux/syscalls.cc 508bbec99e58
src/arch/sparc/process.cc 508bbec99e58
src/arch/sparc/solaris/process.cc 508bbec99e58
src/arch/sparc/system.hh 508bbec99e58
src/arch/sparc/system.cc 508bbec99e58
src/arch/sparc/utility.cc 508bbec99e58
src/arch/sparc/vtophys.cc 508bbec99e58
src/arch/x86/bios/intelmp.hh 508bbec99e58
src/arch/x86/bios/intelmp.cc 508bbec99e58
src/arch/x86/bios/smbios.hh 508bbec99e58
src/arch/x86/bios/smbios.cc 508bbec99e58
src/arch/x86/linux/syscalls.cc 508bbec99e58
src/arch/x86/linux/system.cc 508bbec99e58
src/arch/x86/process.cc 508bbec99e58
src/arch/x86/stacktrace.cc 508bbec99e58
src/arch/x86/system.cc 508bbec99e58
src/base/loader/elf_object.hh 508bbec99e58
src/base/loader/elf_object.cc 508bbec99e58
src/base/loader/hex_file.hh 508bbec99e58
src/base/loader/hex_file.cc 508bbec99e58
src/base/loader/object_file.hh 508bbec99e58
src/base/loader/object_file.cc 508bbec99e58
src/base/remote_gdb.cc 508bbec99e58
src/cpu/checker/thread_context.hh 508bbec99e58
src/cpu/inorder/cpu.hh 508bbec99e58
src/cpu/inorder/cpu.cc 508bbec99e58
src/cpu/inorder/resources/cache_unit.hh 508bbec99e58
src/cpu/inorder/resources/cache_unit.cc 508bbec99e58
src/cpu/inorder/thread_context.hh 508bbec99e58
src/cpu/inorder/thread_context.cc 508bbec99e58
src/cpu/o3/cpu.hh 508bbec99e58
src/cpu/o3/cpu.cc 508bbec99e58
src/cpu/o3/lsq.hh 508bbec99e58
src/cpu/o3/lsq_impl.hh 508bbec99e58
src/cpu/o3/thread_context.hh 508bbec99e58
src/cpu/o3/thread_context_impl.hh 508bbec99e58
src/cpu/ozone/cpu.hh 508bbec99e58
src/cpu/ozone/cpu_impl.hh 508bbec99e58
src/cpu/simple/atomic.hh 508bbec99e58
src/cpu/simple/atomic.cc 508bbec99e58
src/cpu/simple/timing.hh 508bbec99e58
src/cpu/simple/timing.cc 508bbec99e58
src/cpu/simple_thread.hh 508bbec99e58
src/cpu/simple_thread.cc 508bbec99e58
src/cpu/thread_context.hh 508bbec99e58
src/cpu/thread_state.hh 508bbec99e58
src/cpu/thread_state.cc 508bbec99e58
src/dev/simple_disk.cc 508bbec99e58
src/kern/tru64/tru64.hh 508bbec99e58
src/kern/tru64/tru64_events.cc 508bbec99e58
src/mem/SConscript 508bbec99e58
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 508bbec99e58
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 508bbec99e58
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 508bbec99e58
src/mem/ruby/system/Sequencer.py 508bbec99e58
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 508bbec99e58
src/mem/translating_port.cc 508bbec99e58
src/mem/vport.hh 508bbec99e58
src/mem/vport.cc 508bbec99e58
src/sim/arguments.hh 508bbec99e58
src/sim/process.hh 508bbec99e58
src/sim/process.cc 508bbec99e58
src/sim/process_impl.hh 508bbec99e58
src/sim/syscall_emul.hh 508bbec99e58
src/sim/syscall_emul.cc 508bbec99e58
src/sim/system.hh 508bbec99e58
src/sim/system.cc 508bbec99e58
src/sim/vptr.hh 508bbec99e58
tests/configs/inorder-timing.py 508bbec99e58
tests/configs/memtest.py 508bbec99e58
tests/configs/o3-timing-mp.py 508bbec99e58
tests/configs/o3-timing.py 508bbec99e58
tests/configs/simple-atomic-mp.py 508bbec99e58
tests/configs/simple-atomic.py 508bbec99e58
tests/configs/simple-timing-mp-ruby.py 508bbec99e58
tests/configs/simple-timing-mp.py 508bbec99e58
tests/configs/simple-timing-ruby.py 508bbec99e58
tests/configs/simple-timing.py 508bbec99e58
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-13 10:50:07 UTC
Permalink
Post by Andreas Hansson
Post by Steve Reinhardt
Looks pretty good... several comments below (some minor, a couple more significant ones), and there's also the pointer declaration style issue to iron out, but it looks pretty close.
I think this is my last patch to review of your series, Andreas. I think there were only a couple (including this one) I didn't mark as "ship it"... those are the only ones I care to see again before you commit.
Thanks for all your hard work!
Thanks for the review.
diff --git a/src/mem/vport.cc b/src/mem/fs_translating_port_proxy.cc
rename from src/mem/vport.cc
rename to src/mem/fs_translating_port_proxy.cc
--- a/src/mem/vport.cc
+++ b/src/mem/fs_translating_port_proxy.cc
I would suggest to adopt this patch as it is and leave the tidying up for a separate patch. This minimises the changes, even if the reviewboard does not seem to understand the renaming. If we take this approach, is there anything you still want to see changed?


- Andreas


-----------------------------------------------------------
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-----------------------------------------------------------
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-12 10:19:12)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 99ba36eaa789
configs/example/se.py 99ba36eaa789
configs/ruby/Ruby.py 99ba36eaa789
src/arch/alpha/freebsd/system.cc 99ba36eaa789
src/arch/alpha/linux/process.cc 99ba36eaa789
src/arch/alpha/linux/system.hh 99ba36eaa789
src/arch/alpha/linux/system.cc 99ba36eaa789
src/arch/alpha/linux/threadinfo.hh 99ba36eaa789
src/arch/alpha/remote_gdb.cc 99ba36eaa789
src/arch/alpha/stacktrace.cc 99ba36eaa789
src/arch/alpha/system.hh 99ba36eaa789
src/arch/alpha/system.cc 99ba36eaa789
src/arch/alpha/tru64/process.cc 99ba36eaa789
src/arch/alpha/tru64/system.cc 99ba36eaa789
src/arch/alpha/utility.cc 99ba36eaa789
src/arch/alpha/vtophys.hh 99ba36eaa789
src/arch/alpha/vtophys.cc 99ba36eaa789
src/arch/arm/linux/process.cc 99ba36eaa789
src/arch/arm/linux/system.cc 99ba36eaa789
src/arch/arm/process.cc 99ba36eaa789
src/arch/arm/stacktrace.cc 99ba36eaa789
src/arch/arm/system.hh 99ba36eaa789
src/arch/arm/system.cc 99ba36eaa789
src/arch/arm/utility.cc 99ba36eaa789
src/arch/arm/vtophys.cc 99ba36eaa789
src/arch/mips/linux/process.cc 99ba36eaa789
src/arch/mips/linux/system.cc 99ba36eaa789
src/arch/mips/linux/threadinfo.hh 99ba36eaa789
src/arch/mips/stacktrace.cc 99ba36eaa789
src/arch/mips/utility.cc 99ba36eaa789
src/arch/power/linux/process.cc 99ba36eaa789
src/arch/power/process.cc 99ba36eaa789
src/arch/sparc/linux/syscalls.cc 99ba36eaa789
src/arch/sparc/process.cc 99ba36eaa789
src/arch/sparc/solaris/process.cc 99ba36eaa789
src/arch/sparc/system.hh 99ba36eaa789
src/arch/sparc/system.cc 99ba36eaa789
src/arch/sparc/utility.cc 99ba36eaa789
src/arch/sparc/vtophys.cc 99ba36eaa789
src/arch/x86/bios/intelmp.hh 99ba36eaa789
src/arch/x86/bios/intelmp.cc 99ba36eaa789
src/arch/x86/bios/smbios.hh 99ba36eaa789
src/arch/x86/bios/smbios.cc 99ba36eaa789
src/arch/x86/linux/syscalls.cc 99ba36eaa789
src/arch/x86/linux/system.cc 99ba36eaa789
src/arch/x86/process.cc 99ba36eaa789
src/arch/x86/stacktrace.cc 99ba36eaa789
src/arch/x86/system.cc 99ba36eaa789
src/base/loader/elf_object.hh 99ba36eaa789
src/base/loader/elf_object.cc 99ba36eaa789
src/base/loader/hex_file.hh 99ba36eaa789
src/base/loader/hex_file.cc 99ba36eaa789
src/base/loader/object_file.hh 99ba36eaa789
src/base/loader/object_file.cc 99ba36eaa789
src/base/remote_gdb.cc 99ba36eaa789
src/cpu/checker/thread_context.hh 99ba36eaa789
src/cpu/inorder/cpu.hh 99ba36eaa789
src/cpu/inorder/cpu.cc 99ba36eaa789
src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789
src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789
src/cpu/inorder/thread_context.hh 99ba36eaa789
src/cpu/inorder/thread_context.cc 99ba36eaa789
src/cpu/o3/cpu.hh 99ba36eaa789
src/cpu/o3/cpu.cc 99ba36eaa789
src/cpu/o3/lsq.hh 99ba36eaa789
src/cpu/o3/lsq_impl.hh 99ba36eaa789
src/cpu/o3/thread_context.hh 99ba36eaa789
src/cpu/o3/thread_context_impl.hh 99ba36eaa789
src/cpu/ozone/cpu.hh 99ba36eaa789
src/cpu/ozone/cpu_impl.hh 99ba36eaa789
src/cpu/simple/atomic.hh 99ba36eaa789
src/cpu/simple/atomic.cc 99ba36eaa789
src/cpu/simple/timing.hh 99ba36eaa789
src/cpu/simple/timing.cc 99ba36eaa789
src/cpu/simple_thread.hh 99ba36eaa789
src/cpu/simple_thread.cc 99ba36eaa789
src/cpu/thread_context.hh 99ba36eaa789
src/cpu/thread_state.hh 99ba36eaa789
src/cpu/thread_state.cc 99ba36eaa789
src/dev/simple_disk.cc 99ba36eaa789
src/kern/tru64/tru64.hh 99ba36eaa789
src/kern/tru64/tru64_events.cc 99ba36eaa789
src/mem/SConscript 99ba36eaa789
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 99ba36eaa789
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 99ba36eaa789
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 99ba36eaa789
src/mem/ruby/system/Sequencer.py 99ba36eaa789
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 99ba36eaa789
src/mem/translating_port.cc 99ba36eaa789
src/mem/vport.hh 99ba36eaa789
src/mem/vport.cc 99ba36eaa789
src/sim/arguments.hh 99ba36eaa789
src/sim/process.hh 99ba36eaa789
src/sim/process.cc 99ba36eaa789
src/sim/process_impl.hh 99ba36eaa789
src/sim/syscall_emul.hh 99ba36eaa789
src/sim/syscall_emul.cc 99ba36eaa789
src/sim/system.hh 99ba36eaa789
src/sim/system.cc 99ba36eaa789
src/sim/vptr.hh 99ba36eaa789
tests/configs/inorder-timing.py 99ba36eaa789
tests/configs/memtest-ruby.py 99ba36eaa789
tests/configs/memtest.py 99ba36eaa789
tests/configs/o3-timing-mp.py 99ba36eaa789
tests/configs/o3-timing.py 99ba36eaa789
tests/configs/rubytest-ruby.py 99ba36eaa789
tests/configs/simple-atomic-mp.py 99ba36eaa789
tests/configs/simple-atomic.py 99ba36eaa789
tests/configs/simple-timing-mp-ruby.py 99ba36eaa789
tests/configs/simple-timing-mp.py 99ba36eaa789
tests/configs/simple-timing-ruby.py 99ba36eaa789
tests/configs/simple-timing.py 99ba36eaa789
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-12 18:19:12 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-12 10:19:12.409593)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py 99ba36eaa789
configs/example/se.py 99ba36eaa789
configs/ruby/Ruby.py 99ba36eaa789
src/arch/alpha/freebsd/system.cc 99ba36eaa789
src/arch/alpha/linux/process.cc 99ba36eaa789
src/arch/alpha/linux/system.hh 99ba36eaa789
src/arch/alpha/linux/system.cc 99ba36eaa789
src/arch/alpha/linux/threadinfo.hh 99ba36eaa789
src/arch/alpha/remote_gdb.cc 99ba36eaa789
src/arch/alpha/stacktrace.cc 99ba36eaa789
src/arch/alpha/system.hh 99ba36eaa789
src/arch/alpha/system.cc 99ba36eaa789
src/arch/alpha/tru64/process.cc 99ba36eaa789
src/arch/alpha/tru64/system.cc 99ba36eaa789
src/arch/alpha/utility.cc 99ba36eaa789
src/arch/alpha/vtophys.hh 99ba36eaa789
src/arch/alpha/vtophys.cc 99ba36eaa789
src/arch/arm/linux/process.cc 99ba36eaa789
src/arch/arm/linux/system.cc 99ba36eaa789
src/arch/arm/process.cc 99ba36eaa789
src/arch/arm/stacktrace.cc 99ba36eaa789
src/arch/arm/system.hh 99ba36eaa789
src/arch/arm/system.cc 99ba36eaa789
src/arch/arm/utility.cc 99ba36eaa789
src/arch/arm/vtophys.cc 99ba36eaa789
src/arch/mips/linux/process.cc 99ba36eaa789
src/arch/mips/linux/system.cc 99ba36eaa789
src/arch/mips/linux/threadinfo.hh 99ba36eaa789
src/arch/mips/stacktrace.cc 99ba36eaa789
src/arch/mips/utility.cc 99ba36eaa789
src/arch/power/linux/process.cc 99ba36eaa789
src/arch/power/process.cc 99ba36eaa789
src/arch/sparc/linux/syscalls.cc 99ba36eaa789
src/arch/sparc/process.cc 99ba36eaa789
src/arch/sparc/solaris/process.cc 99ba36eaa789
src/arch/sparc/system.hh 99ba36eaa789
src/arch/sparc/system.cc 99ba36eaa789
src/arch/sparc/utility.cc 99ba36eaa789
src/arch/sparc/vtophys.cc 99ba36eaa789
src/arch/x86/bios/intelmp.hh 99ba36eaa789
src/arch/x86/bios/intelmp.cc 99ba36eaa789
src/arch/x86/bios/smbios.hh 99ba36eaa789
src/arch/x86/bios/smbios.cc 99ba36eaa789
src/arch/x86/linux/syscalls.cc 99ba36eaa789
src/arch/x86/linux/system.cc 99ba36eaa789
src/arch/x86/process.cc 99ba36eaa789
src/arch/x86/stacktrace.cc 99ba36eaa789
src/arch/x86/system.cc 99ba36eaa789
src/base/loader/elf_object.hh 99ba36eaa789
src/base/loader/elf_object.cc 99ba36eaa789
src/base/loader/hex_file.hh 99ba36eaa789
src/base/loader/hex_file.cc 99ba36eaa789
src/base/loader/object_file.hh 99ba36eaa789
src/base/loader/object_file.cc 99ba36eaa789
src/base/remote_gdb.cc 99ba36eaa789
src/cpu/checker/thread_context.hh 99ba36eaa789
src/cpu/inorder/cpu.hh 99ba36eaa789
src/cpu/inorder/cpu.cc 99ba36eaa789
src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789
src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789
src/cpu/inorder/thread_context.hh 99ba36eaa789
src/cpu/inorder/thread_context.cc 99ba36eaa789
src/cpu/o3/cpu.hh 99ba36eaa789
src/cpu/o3/cpu.cc 99ba36eaa789
src/cpu/o3/lsq.hh 99ba36eaa789
src/cpu/o3/lsq_impl.hh 99ba36eaa789
src/cpu/o3/thread_context.hh 99ba36eaa789
src/cpu/o3/thread_context_impl.hh 99ba36eaa789
src/cpu/ozone/cpu.hh 99ba36eaa789
src/cpu/ozone/cpu_impl.hh 99ba36eaa789
src/cpu/simple/atomic.hh 99ba36eaa789
src/cpu/simple/atomic.cc 99ba36eaa789
src/cpu/simple/timing.hh 99ba36eaa789
src/cpu/simple/timing.cc 99ba36eaa789
src/cpu/simple_thread.hh 99ba36eaa789
src/cpu/simple_thread.cc 99ba36eaa789
src/cpu/thread_context.hh 99ba36eaa789
src/cpu/thread_state.hh 99ba36eaa789
src/cpu/thread_state.cc 99ba36eaa789
src/dev/simple_disk.cc 99ba36eaa789
src/kern/tru64/tru64.hh 99ba36eaa789
src/kern/tru64/tru64_events.cc 99ba36eaa789
src/mem/SConscript 99ba36eaa789
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 99ba36eaa789
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 99ba36eaa789
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 99ba36eaa789
src/mem/ruby/system/Sequencer.py 99ba36eaa789
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 99ba36eaa789
src/mem/translating_port.cc 99ba36eaa789
src/mem/vport.hh 99ba36eaa789
src/mem/vport.cc 99ba36eaa789
src/sim/arguments.hh 99ba36eaa789
src/sim/process.hh 99ba36eaa789
src/sim/process.cc 99ba36eaa789
src/sim/process_impl.hh 99ba36eaa789
src/sim/syscall_emul.hh 99ba36eaa789
src/sim/syscall_emul.cc 99ba36eaa789
src/sim/system.hh 99ba36eaa789
src/sim/system.cc 99ba36eaa789
src/sim/vptr.hh 99ba36eaa789
tests/configs/inorder-timing.py 99ba36eaa789
tests/configs/memtest-ruby.py 99ba36eaa789
tests/configs/memtest.py 99ba36eaa789
tests/configs/o3-timing-mp.py 99ba36eaa789
tests/configs/o3-timing.py 99ba36eaa789
tests/configs/rubytest-ruby.py 99ba36eaa789
tests/configs/simple-atomic-mp.py 99ba36eaa789
tests/configs/simple-atomic.py 99ba36eaa789
tests/configs/simple-timing-mp-ruby.py 99ba36eaa789
tests/configs/simple-timing-mp.py 99ba36eaa789
tests/configs/simple-timing-ruby.py 99ba36eaa789
tests/configs/simple-timing.py 99ba36eaa789

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Steve Reinhardt
2012-01-13 16:51:34 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/#review1942
-----------------------------------------------------------


Sorry about nagging you on the file renames; it didn't occur to me that perhaps you had fixed that and reviewboard just wasn't capable of showing it. Also I agree on saving the little things that are carryovers from the old code for a separate patch (the comma spacing and the translate() helper function); since reviewboard wasn't showing the rename properly it wasn't obvious that these issues were also there in the old code.

The one thing I am still concerned about is the read*() and write*() methods on FSTranslatingPortProxy. It seems like those aren't necessary (since VirtualPort doesn't have them) and the current implementations aren't correct (since they don't deal with page crossings), so I'd prefer to see those just left out until we put in working ones. In the meantime, the even-more-broken PortProxy methods will get inherited and not overridden; if we care about that, maybe we should temporarily override them with methods that panic. (If we had C++11 we could delete them...)

- Steve
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-12 10:19:12)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 99ba36eaa789
configs/example/se.py 99ba36eaa789
configs/ruby/Ruby.py 99ba36eaa789
src/arch/alpha/freebsd/system.cc 99ba36eaa789
src/arch/alpha/linux/process.cc 99ba36eaa789
src/arch/alpha/linux/system.hh 99ba36eaa789
src/arch/alpha/linux/system.cc 99ba36eaa789
src/arch/alpha/linux/threadinfo.hh 99ba36eaa789
src/arch/alpha/remote_gdb.cc 99ba36eaa789
src/arch/alpha/stacktrace.cc 99ba36eaa789
src/arch/alpha/system.hh 99ba36eaa789
src/arch/alpha/system.cc 99ba36eaa789
src/arch/alpha/tru64/process.cc 99ba36eaa789
src/arch/alpha/tru64/system.cc 99ba36eaa789
src/arch/alpha/utility.cc 99ba36eaa789
src/arch/alpha/vtophys.hh 99ba36eaa789
src/arch/alpha/vtophys.cc 99ba36eaa789
src/arch/arm/linux/process.cc 99ba36eaa789
src/arch/arm/linux/system.cc 99ba36eaa789
src/arch/arm/process.cc 99ba36eaa789
src/arch/arm/stacktrace.cc 99ba36eaa789
src/arch/arm/system.hh 99ba36eaa789
src/arch/arm/system.cc 99ba36eaa789
src/arch/arm/utility.cc 99ba36eaa789
src/arch/arm/vtophys.cc 99ba36eaa789
src/arch/mips/linux/process.cc 99ba36eaa789
src/arch/mips/linux/system.cc 99ba36eaa789
src/arch/mips/linux/threadinfo.hh 99ba36eaa789
src/arch/mips/stacktrace.cc 99ba36eaa789
src/arch/mips/utility.cc 99ba36eaa789
src/arch/power/linux/process.cc 99ba36eaa789
src/arch/power/process.cc 99ba36eaa789
src/arch/sparc/linux/syscalls.cc 99ba36eaa789
src/arch/sparc/process.cc 99ba36eaa789
src/arch/sparc/solaris/process.cc 99ba36eaa789
src/arch/sparc/system.hh 99ba36eaa789
src/arch/sparc/system.cc 99ba36eaa789
src/arch/sparc/utility.cc 99ba36eaa789
src/arch/sparc/vtophys.cc 99ba36eaa789
src/arch/x86/bios/intelmp.hh 99ba36eaa789
src/arch/x86/bios/intelmp.cc 99ba36eaa789
src/arch/x86/bios/smbios.hh 99ba36eaa789
src/arch/x86/bios/smbios.cc 99ba36eaa789
src/arch/x86/linux/syscalls.cc 99ba36eaa789
src/arch/x86/linux/system.cc 99ba36eaa789
src/arch/x86/process.cc 99ba36eaa789
src/arch/x86/stacktrace.cc 99ba36eaa789
src/arch/x86/system.cc 99ba36eaa789
src/base/loader/elf_object.hh 99ba36eaa789
src/base/loader/elf_object.cc 99ba36eaa789
src/base/loader/hex_file.hh 99ba36eaa789
src/base/loader/hex_file.cc 99ba36eaa789
src/base/loader/object_file.hh 99ba36eaa789
src/base/loader/object_file.cc 99ba36eaa789
src/base/remote_gdb.cc 99ba36eaa789
src/cpu/checker/thread_context.hh 99ba36eaa789
src/cpu/inorder/cpu.hh 99ba36eaa789
src/cpu/inorder/cpu.cc 99ba36eaa789
src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789
src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789
src/cpu/inorder/thread_context.hh 99ba36eaa789
src/cpu/inorder/thread_context.cc 99ba36eaa789
src/cpu/o3/cpu.hh 99ba36eaa789
src/cpu/o3/cpu.cc 99ba36eaa789
src/cpu/o3/lsq.hh 99ba36eaa789
src/cpu/o3/lsq_impl.hh 99ba36eaa789
src/cpu/o3/thread_context.hh 99ba36eaa789
src/cpu/o3/thread_context_impl.hh 99ba36eaa789
src/cpu/ozone/cpu.hh 99ba36eaa789
src/cpu/ozone/cpu_impl.hh 99ba36eaa789
src/cpu/simple/atomic.hh 99ba36eaa789
src/cpu/simple/atomic.cc 99ba36eaa789
src/cpu/simple/timing.hh 99ba36eaa789
src/cpu/simple/timing.cc 99ba36eaa789
src/cpu/simple_thread.hh 99ba36eaa789
src/cpu/simple_thread.cc 99ba36eaa789
src/cpu/thread_context.hh 99ba36eaa789
src/cpu/thread_state.hh 99ba36eaa789
src/cpu/thread_state.cc 99ba36eaa789
src/dev/simple_disk.cc 99ba36eaa789
src/kern/tru64/tru64.hh 99ba36eaa789
src/kern/tru64/tru64_events.cc 99ba36eaa789
src/mem/SConscript 99ba36eaa789
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 99ba36eaa789
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 99ba36eaa789
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 99ba36eaa789
src/mem/ruby/system/Sequencer.py 99ba36eaa789
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 99ba36eaa789
src/mem/translating_port.cc 99ba36eaa789
src/mem/vport.hh 99ba36eaa789
src/mem/vport.cc 99ba36eaa789
src/sim/arguments.hh 99ba36eaa789
src/sim/process.hh 99ba36eaa789
src/sim/process.cc 99ba36eaa789
src/sim/process_impl.hh 99ba36eaa789
src/sim/syscall_emul.hh 99ba36eaa789
src/sim/syscall_emul.cc 99ba36eaa789
src/sim/system.hh 99ba36eaa789
src/sim/system.cc 99ba36eaa789
src/sim/vptr.hh 99ba36eaa789
tests/configs/inorder-timing.py 99ba36eaa789
tests/configs/memtest-ruby.py 99ba36eaa789
tests/configs/memtest.py 99ba36eaa789
tests/configs/o3-timing-mp.py 99ba36eaa789
tests/configs/o3-timing.py 99ba36eaa789
tests/configs/rubytest-ruby.py 99ba36eaa789
tests/configs/simple-atomic-mp.py 99ba36eaa789
tests/configs/simple-atomic.py 99ba36eaa789
tests/configs/simple-timing-mp-ruby.py 99ba36eaa789
tests/configs/simple-timing-mp.py 99ba36eaa789
tests/configs/simple-timing-ruby.py 99ba36eaa789
tests/configs/simple-timing.py 99ba36eaa789
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-13 16:57:30 UTC
Permalink
Post by Andreas Hansson
Post by Steve Reinhardt
Sorry about nagging you on the file renames; it didn't occur to me that perhaps you had fixed that and reviewboard just wasn't capable of showing it. Also I agree on saving the little things that are carryovers from the old code for a separate patch (the comma spacing and the translate() helper function); since reviewboard wasn't showing the rename properly it wasn't obvious that these issues were also there in the old code.
The one thing I am still concerned about is the read*() and write*() methods on FSTranslatingPortProxy. It seems like those aren't necessary (since VirtualPort doesn't have them) and the current implementations aren't correct (since they don't deal with page crossings), so I'd prefer to see those just left out until we put in working ones. In the meantime, the even-more-broken PortProxy methods will get inherited and not overridden; if we care about that, maybe we should temporarily override them with methods that panic. (If we had C++11 we could delete them...)
No problem...I'm getting used to reviewboard oddities :)

I see what you are saying about the readGtoH/readHtoG and writeGtoH/writeHtoG and will make an attempt at removing them and see what the outcome is on the regressions.


- Andreas


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Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-12 10:19:12)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py 99ba36eaa789
configs/example/se.py 99ba36eaa789
configs/ruby/Ruby.py 99ba36eaa789
src/arch/alpha/freebsd/system.cc 99ba36eaa789
src/arch/alpha/linux/process.cc 99ba36eaa789
src/arch/alpha/linux/system.hh 99ba36eaa789
src/arch/alpha/linux/system.cc 99ba36eaa789
src/arch/alpha/linux/threadinfo.hh 99ba36eaa789
src/arch/alpha/remote_gdb.cc 99ba36eaa789
src/arch/alpha/stacktrace.cc 99ba36eaa789
src/arch/alpha/system.hh 99ba36eaa789
src/arch/alpha/system.cc 99ba36eaa789
src/arch/alpha/tru64/process.cc 99ba36eaa789
src/arch/alpha/tru64/system.cc 99ba36eaa789
src/arch/alpha/utility.cc 99ba36eaa789
src/arch/alpha/vtophys.hh 99ba36eaa789
src/arch/alpha/vtophys.cc 99ba36eaa789
src/arch/arm/linux/process.cc 99ba36eaa789
src/arch/arm/linux/system.cc 99ba36eaa789
src/arch/arm/process.cc 99ba36eaa789
src/arch/arm/stacktrace.cc 99ba36eaa789
src/arch/arm/system.hh 99ba36eaa789
src/arch/arm/system.cc 99ba36eaa789
src/arch/arm/utility.cc 99ba36eaa789
src/arch/arm/vtophys.cc 99ba36eaa789
src/arch/mips/linux/process.cc 99ba36eaa789
src/arch/mips/linux/system.cc 99ba36eaa789
src/arch/mips/linux/threadinfo.hh 99ba36eaa789
src/arch/mips/stacktrace.cc 99ba36eaa789
src/arch/mips/utility.cc 99ba36eaa789
src/arch/power/linux/process.cc 99ba36eaa789
src/arch/power/process.cc 99ba36eaa789
src/arch/sparc/linux/syscalls.cc 99ba36eaa789
src/arch/sparc/process.cc 99ba36eaa789
src/arch/sparc/solaris/process.cc 99ba36eaa789
src/arch/sparc/system.hh 99ba36eaa789
src/arch/sparc/system.cc 99ba36eaa789
src/arch/sparc/utility.cc 99ba36eaa789
src/arch/sparc/vtophys.cc 99ba36eaa789
src/arch/x86/bios/intelmp.hh 99ba36eaa789
src/arch/x86/bios/intelmp.cc 99ba36eaa789
src/arch/x86/bios/smbios.hh 99ba36eaa789
src/arch/x86/bios/smbios.cc 99ba36eaa789
src/arch/x86/linux/syscalls.cc 99ba36eaa789
src/arch/x86/linux/system.cc 99ba36eaa789
src/arch/x86/process.cc 99ba36eaa789
src/arch/x86/stacktrace.cc 99ba36eaa789
src/arch/x86/system.cc 99ba36eaa789
src/base/loader/elf_object.hh 99ba36eaa789
src/base/loader/elf_object.cc 99ba36eaa789
src/base/loader/hex_file.hh 99ba36eaa789
src/base/loader/hex_file.cc 99ba36eaa789
src/base/loader/object_file.hh 99ba36eaa789
src/base/loader/object_file.cc 99ba36eaa789
src/base/remote_gdb.cc 99ba36eaa789
src/cpu/checker/thread_context.hh 99ba36eaa789
src/cpu/inorder/cpu.hh 99ba36eaa789
src/cpu/inorder/cpu.cc 99ba36eaa789
src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789
src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789
src/cpu/inorder/thread_context.hh 99ba36eaa789
src/cpu/inorder/thread_context.cc 99ba36eaa789
src/cpu/o3/cpu.hh 99ba36eaa789
src/cpu/o3/cpu.cc 99ba36eaa789
src/cpu/o3/lsq.hh 99ba36eaa789
src/cpu/o3/lsq_impl.hh 99ba36eaa789
src/cpu/o3/thread_context.hh 99ba36eaa789
src/cpu/o3/thread_context_impl.hh 99ba36eaa789
src/cpu/ozone/cpu.hh 99ba36eaa789
src/cpu/ozone/cpu_impl.hh 99ba36eaa789
src/cpu/simple/atomic.hh 99ba36eaa789
src/cpu/simple/atomic.cc 99ba36eaa789
src/cpu/simple/timing.hh 99ba36eaa789
src/cpu/simple/timing.cc 99ba36eaa789
src/cpu/simple_thread.hh 99ba36eaa789
src/cpu/simple_thread.cc 99ba36eaa789
src/cpu/thread_context.hh 99ba36eaa789
src/cpu/thread_state.hh 99ba36eaa789
src/cpu/thread_state.cc 99ba36eaa789
src/dev/simple_disk.cc 99ba36eaa789
src/kern/tru64/tru64.hh 99ba36eaa789
src/kern/tru64/tru64_events.cc 99ba36eaa789
src/mem/SConscript 99ba36eaa789
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh 99ba36eaa789
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc 99ba36eaa789
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript 99ba36eaa789
src/mem/ruby/system/Sequencer.py 99ba36eaa789
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh 99ba36eaa789
src/mem/translating_port.cc 99ba36eaa789
src/mem/vport.hh 99ba36eaa789
src/mem/vport.cc 99ba36eaa789
src/sim/arguments.hh 99ba36eaa789
src/sim/process.hh 99ba36eaa789
src/sim/process.cc 99ba36eaa789
src/sim/process_impl.hh 99ba36eaa789
src/sim/syscall_emul.hh 99ba36eaa789
src/sim/syscall_emul.cc 99ba36eaa789
src/sim/system.hh 99ba36eaa789
src/sim/system.cc 99ba36eaa789
src/sim/vptr.hh 99ba36eaa789
tests/configs/inorder-timing.py 99ba36eaa789
tests/configs/memtest-ruby.py 99ba36eaa789
tests/configs/memtest.py 99ba36eaa789
tests/configs/o3-timing-mp.py 99ba36eaa789
tests/configs/o3-timing.py 99ba36eaa789
tests/configs/rubytest-ruby.py 99ba36eaa789
tests/configs/simple-atomic-mp.py 99ba36eaa789
tests/configs/simple-atomic.py 99ba36eaa789
tests/configs/simple-timing-mp-ruby.py 99ba36eaa789
tests/configs/simple-timing-mp.py 99ba36eaa789
tests/configs/simple-timing-ruby.py 99ba36eaa789
tests/configs/simple-timing.py 99ba36eaa789
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
Andreas Hansson
2012-01-13 18:24:11 UTC
Permalink
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------

(Updated 2012-01-13 10:24:11.388932)


Review request for Default.


Summary
-------

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


Diffs (updated)
-----

configs/common/FSConfig.py f348cf78072c
configs/example/se.py f348cf78072c
configs/ruby/Ruby.py f348cf78072c
src/arch/alpha/freebsd/system.cc f348cf78072c
src/arch/alpha/linux/process.cc f348cf78072c
src/arch/alpha/linux/system.hh f348cf78072c
src/arch/alpha/linux/system.cc f348cf78072c
src/arch/alpha/linux/threadinfo.hh f348cf78072c
src/arch/alpha/remote_gdb.cc f348cf78072c
src/arch/alpha/stacktrace.cc f348cf78072c
src/arch/alpha/system.hh f348cf78072c
src/arch/alpha/system.cc f348cf78072c
src/arch/alpha/tru64/process.cc f348cf78072c
src/arch/alpha/tru64/system.cc f348cf78072c
src/arch/alpha/utility.cc f348cf78072c
src/arch/alpha/vtophys.hh f348cf78072c
src/arch/alpha/vtophys.cc f348cf78072c
src/arch/arm/linux/process.cc f348cf78072c
src/arch/arm/linux/system.cc f348cf78072c
src/arch/arm/process.cc f348cf78072c
src/arch/arm/stacktrace.cc f348cf78072c
src/arch/arm/system.hh f348cf78072c
src/arch/arm/system.cc f348cf78072c
src/arch/arm/utility.cc f348cf78072c
src/arch/arm/vtophys.cc f348cf78072c
src/arch/mips/linux/process.cc f348cf78072c
src/arch/mips/linux/system.cc f348cf78072c
src/arch/mips/linux/threadinfo.hh f348cf78072c
src/arch/mips/stacktrace.cc f348cf78072c
src/arch/mips/utility.cc f348cf78072c
src/arch/power/linux/process.cc f348cf78072c
src/arch/power/process.cc f348cf78072c
src/arch/sparc/linux/syscalls.cc f348cf78072c
src/arch/sparc/process.cc f348cf78072c
src/arch/sparc/solaris/process.cc f348cf78072c
src/arch/sparc/system.hh f348cf78072c
src/arch/sparc/system.cc f348cf78072c
src/arch/sparc/utility.cc f348cf78072c
src/arch/sparc/vtophys.cc f348cf78072c
src/arch/x86/bios/intelmp.hh f348cf78072c
src/arch/x86/bios/intelmp.cc f348cf78072c
src/arch/x86/bios/smbios.hh f348cf78072c
src/arch/x86/bios/smbios.cc f348cf78072c
src/arch/x86/linux/syscalls.cc f348cf78072c
src/arch/x86/linux/system.cc f348cf78072c
src/arch/x86/process.cc f348cf78072c
src/arch/x86/stacktrace.cc f348cf78072c
src/arch/x86/system.cc f348cf78072c
src/base/loader/elf_object.hh f348cf78072c
src/base/loader/elf_object.cc f348cf78072c
src/base/loader/hex_file.hh f348cf78072c
src/base/loader/hex_file.cc f348cf78072c
src/base/loader/object_file.hh f348cf78072c
src/base/loader/object_file.cc f348cf78072c
src/base/remote_gdb.cc f348cf78072c
src/cpu/checker/thread_context.hh f348cf78072c
src/cpu/inorder/cpu.hh f348cf78072c
src/cpu/inorder/cpu.cc f348cf78072c
src/cpu/inorder/resources/cache_unit.hh f348cf78072c
src/cpu/inorder/resources/cache_unit.cc f348cf78072c
src/cpu/inorder/thread_context.hh f348cf78072c
src/cpu/inorder/thread_context.cc f348cf78072c
src/cpu/o3/cpu.hh f348cf78072c
src/cpu/o3/cpu.cc f348cf78072c
src/cpu/o3/lsq.hh f348cf78072c
src/cpu/o3/lsq_impl.hh f348cf78072c
src/cpu/o3/thread_context.hh f348cf78072c
src/cpu/o3/thread_context_impl.hh f348cf78072c
src/cpu/ozone/cpu.hh f348cf78072c
src/cpu/ozone/cpu_impl.hh f348cf78072c
src/cpu/simple/atomic.hh f348cf78072c
src/cpu/simple/atomic.cc f348cf78072c
src/cpu/simple/timing.hh f348cf78072c
src/cpu/simple/timing.cc f348cf78072c
src/cpu/simple_thread.hh f348cf78072c
src/cpu/simple_thread.cc f348cf78072c
src/cpu/thread_context.hh f348cf78072c
src/cpu/thread_state.hh f348cf78072c
src/cpu/thread_state.cc f348cf78072c
src/dev/simple_disk.cc f348cf78072c
src/kern/tru64/tru64.hh f348cf78072c
src/kern/tru64/tru64_events.cc f348cf78072c
src/mem/SConscript f348cf78072c
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh f348cf78072c
src/mem/port_impl.hh f348cf78072c
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc f348cf78072c
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript f348cf78072c
src/mem/ruby/system/Sequencer.py f348cf78072c
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh f348cf78072c
src/mem/translating_port.cc f348cf78072c
src/mem/vport.hh f348cf78072c
src/mem/vport.cc f348cf78072c
src/sim/arguments.hh f348cf78072c
src/sim/process.hh f348cf78072c
src/sim/process.cc f348cf78072c
src/sim/process_impl.hh f348cf78072c
src/sim/syscall_emul.hh f348cf78072c
src/sim/syscall_emul.cc f348cf78072c
src/sim/system.hh f348cf78072c
src/sim/system.cc f348cf78072c
src/sim/vptr.hh f348cf78072c
tests/configs/inorder-timing.py f348cf78072c
tests/configs/memtest-ruby.py f348cf78072c
tests/configs/memtest.py f348cf78072c
tests/configs/o3-timing-mp.py f348cf78072c
tests/configs/o3-timing.py f348cf78072c
tests/configs/rubytest-ruby.py f348cf78072c
tests/configs/simple-atomic-mp.py f348cf78072c
tests/configs/simple-atomic.py f348cf78072c
tests/configs/simple-timing-mp-ruby.py f348cf78072c
tests/configs/simple-timing-mp.py f348cf78072c
tests/configs/simple-timing-ruby.py f348cf78072c
tests/configs/simple-timing.py f348cf78072c

Diff: http://reviews.m5sim.org/r/943/diff


Testing
-------

util/regress all passing (disregarding t1000 and eio)


Thanks,

Andreas
Steve Reinhardt
2012-01-13 18:32:05 UTC
Permalink
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http://reviews.m5sim.org/r/943/#review1944
-----------------------------------------------------------

Ship it!


I thought you were going to inline the code in port_proxy.cc and get rid of that file... that's not critical though.

Great job! I think that's all the patches, right?

- Steve
Post by Andreas Hansson
-----------------------------------------------------------
http://reviews.m5sim.org/r/943/
-----------------------------------------------------------
(Updated 2012-01-13 10:24:11)
Review request for Default.
Summary
-------
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
Diffs
-----
configs/common/FSConfig.py f348cf78072c
configs/example/se.py f348cf78072c
configs/ruby/Ruby.py f348cf78072c
src/arch/alpha/freebsd/system.cc f348cf78072c
src/arch/alpha/linux/process.cc f348cf78072c
src/arch/alpha/linux/system.hh f348cf78072c
src/arch/alpha/linux/system.cc f348cf78072c
src/arch/alpha/linux/threadinfo.hh f348cf78072c
src/arch/alpha/remote_gdb.cc f348cf78072c
src/arch/alpha/stacktrace.cc f348cf78072c
src/arch/alpha/system.hh f348cf78072c
src/arch/alpha/system.cc f348cf78072c
src/arch/alpha/tru64/process.cc f348cf78072c
src/arch/alpha/tru64/system.cc f348cf78072c
src/arch/alpha/utility.cc f348cf78072c
src/arch/alpha/vtophys.hh f348cf78072c
src/arch/alpha/vtophys.cc f348cf78072c
src/arch/arm/linux/process.cc f348cf78072c
src/arch/arm/linux/system.cc f348cf78072c
src/arch/arm/process.cc f348cf78072c
src/arch/arm/stacktrace.cc f348cf78072c
src/arch/arm/system.hh f348cf78072c
src/arch/arm/system.cc f348cf78072c
src/arch/arm/utility.cc f348cf78072c
src/arch/arm/vtophys.cc f348cf78072c
src/arch/mips/linux/process.cc f348cf78072c
src/arch/mips/linux/system.cc f348cf78072c
src/arch/mips/linux/threadinfo.hh f348cf78072c
src/arch/mips/stacktrace.cc f348cf78072c
src/arch/mips/utility.cc f348cf78072c
src/arch/power/linux/process.cc f348cf78072c
src/arch/power/process.cc f348cf78072c
src/arch/sparc/linux/syscalls.cc f348cf78072c
src/arch/sparc/process.cc f348cf78072c
src/arch/sparc/solaris/process.cc f348cf78072c
src/arch/sparc/system.hh f348cf78072c
src/arch/sparc/system.cc f348cf78072c
src/arch/sparc/utility.cc f348cf78072c
src/arch/sparc/vtophys.cc f348cf78072c
src/arch/x86/bios/intelmp.hh f348cf78072c
src/arch/x86/bios/intelmp.cc f348cf78072c
src/arch/x86/bios/smbios.hh f348cf78072c
src/arch/x86/bios/smbios.cc f348cf78072c
src/arch/x86/linux/syscalls.cc f348cf78072c
src/arch/x86/linux/system.cc f348cf78072c
src/arch/x86/process.cc f348cf78072c
src/arch/x86/stacktrace.cc f348cf78072c
src/arch/x86/system.cc f348cf78072c
src/base/loader/elf_object.hh f348cf78072c
src/base/loader/elf_object.cc f348cf78072c
src/base/loader/hex_file.hh f348cf78072c
src/base/loader/hex_file.cc f348cf78072c
src/base/loader/object_file.hh f348cf78072c
src/base/loader/object_file.cc f348cf78072c
src/base/remote_gdb.cc f348cf78072c
src/cpu/checker/thread_context.hh f348cf78072c
src/cpu/inorder/cpu.hh f348cf78072c
src/cpu/inorder/cpu.cc f348cf78072c
src/cpu/inorder/resources/cache_unit.hh f348cf78072c
src/cpu/inorder/resources/cache_unit.cc f348cf78072c
src/cpu/inorder/thread_context.hh f348cf78072c
src/cpu/inorder/thread_context.cc f348cf78072c
src/cpu/o3/cpu.hh f348cf78072c
src/cpu/o3/cpu.cc f348cf78072c
src/cpu/o3/lsq.hh f348cf78072c
src/cpu/o3/lsq_impl.hh f348cf78072c
src/cpu/o3/thread_context.hh f348cf78072c
src/cpu/o3/thread_context_impl.hh f348cf78072c
src/cpu/ozone/cpu.hh f348cf78072c
src/cpu/ozone/cpu_impl.hh f348cf78072c
src/cpu/simple/atomic.hh f348cf78072c
src/cpu/simple/atomic.cc f348cf78072c
src/cpu/simple/timing.hh f348cf78072c
src/cpu/simple/timing.cc f348cf78072c
src/cpu/simple_thread.hh f348cf78072c
src/cpu/simple_thread.cc f348cf78072c
src/cpu/thread_context.hh f348cf78072c
src/cpu/thread_state.hh f348cf78072c
src/cpu/thread_state.cc f348cf78072c
src/dev/simple_disk.cc f348cf78072c
src/kern/tru64/tru64.hh f348cf78072c
src/kern/tru64/tru64_events.cc f348cf78072c
src/mem/SConscript f348cf78072c
src/mem/fs_translating_port_proxy.hh PRE-CREATION
src/mem/fs_translating_port_proxy.cc PRE-CREATION
src/mem/port.hh f348cf78072c
src/mem/port_impl.hh f348cf78072c
src/mem/port_proxy.hh PRE-CREATION
src/mem/port_proxy.cc PRE-CREATION
src/mem/ruby/system/RubyPort.cc f348cf78072c
src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION
src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION
src/mem/ruby/system/SConscript f348cf78072c
src/mem/ruby/system/Sequencer.py f348cf78072c
src/mem/se_translating_port_proxy.hh PRE-CREATION
src/mem/se_translating_port_proxy.cc PRE-CREATION
src/mem/translating_port.hh f348cf78072c
src/mem/translating_port.cc f348cf78072c
src/mem/vport.hh f348cf78072c
src/mem/vport.cc f348cf78072c
src/sim/arguments.hh f348cf78072c
src/sim/process.hh f348cf78072c
src/sim/process.cc f348cf78072c
src/sim/process_impl.hh f348cf78072c
src/sim/syscall_emul.hh f348cf78072c
src/sim/syscall_emul.cc f348cf78072c
src/sim/system.hh f348cf78072c
src/sim/system.cc f348cf78072c
src/sim/vptr.hh f348cf78072c
tests/configs/inorder-timing.py f348cf78072c
tests/configs/memtest-ruby.py f348cf78072c
tests/configs/memtest.py f348cf78072c
tests/configs/o3-timing-mp.py f348cf78072c
tests/configs/o3-timing.py f348cf78072c
tests/configs/rubytest-ruby.py f348cf78072c
tests/configs/simple-atomic-mp.py f348cf78072c
tests/configs/simple-atomic.py f348cf78072c
tests/configs/simple-timing-mp-ruby.py f348cf78072c
tests/configs/simple-timing-mp.py f348cf78072c
tests/configs/simple-timing-ruby.py f348cf78072c
tests/configs/simple-timing.py f348cf78072c
Diff: http://reviews.m5sim.org/r/943/diff
Testing
-------
util/regress all passing (disregarding t1000 and eio)
Thanks,
Andreas
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