Discussion:
[gem5-dev] changeset in gem5: misc: Clean up and complete the gem5<->System...
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Christian Menard
2017-02-10 17:38:59 UTC
Permalink
changeset f12963cb9dc2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f12963cb9dc2
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

configs/common/MemConfig.py | 2 +-
util/tlm/Makefile | 76 -----
util/tlm/examples/slave_port/SConstruct | 77 +++++
util/tlm/examples/slave_port/main.cc | 115 ++++++++
util/tlm/examples/slave_port/run_gem5.sh | 53 +++
util/tlm/examples/slave_port/sc_target.cc | 264 +++++++++++++++++++
util/tlm/examples/slave_port/sc_target.hh | 100 +++++++
util/tlm/examples/slave_port/tgen.cfg | 57 ++++
util/tlm/examples/slave_port/tlm.py | 78 +++++
util/tlm/examples/slave_port/tlm_elastic.py | 123 +++++++++
util/tlm/main.cc | 331 ------------------------
util/tlm/run_gem5.sh | 53 ---
util/tlm/sc_ext.cc | 27 +-
util/tlm/sc_ext.hh | 21 +-
util/tlm/sc_mm.cc | 5 +
util/tlm/sc_mm.hh | 11 +-
util/tlm/sc_peq.hh | 102 +++++++
util/tlm/sc_port.cc | 372 ---------------------------
util/tlm/sc_port.hh | 174 -------------
util/tlm/sc_slave_port.cc | 374 ++++++++++++++++++++++++++++
util/tlm/sc_slave_port.hh | 129 +++++++++
util/tlm/sc_target.cc | 264 -------------------
util/tlm/sc_target.hh | 100 -------
util/tlm/sim_control.cc | 226 ++++++++++++++++
util/tlm/sim_control.hh | 76 +++++
util/tlm/tgen.cfg | 57 ----
util/tlm/tlm.py | 78 -----
util/tlm/tlm_elastic.py | 123 ---------
28 files changed, 1820 insertions(+), 1648 deletions(-)

diffs (truncated from 3680 to 300 lines):

diff -r 594d96c093d0 -r f12963cb9dc2 configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Thu Feb 09 19:14:58 2017 -0500
+++ b/configs/common/MemConfig.py Thu Feb 09 19:15:30 2017 -0500
@@ -163,7 +163,7 @@

if options.tlm_memory:
system.external_memory = m5.objects.ExternalSlave(
- port_type="tlm",
+ port_type="tlm_slave",
port_data=options.tlm_memory,
port=system.membus.master,
addr_ranges=system.mem_ranges)
diff -r 594d96c093d0 -r f12963cb9dc2 util/tlm/Makefile
--- a/util/tlm/Makefile Thu Feb 09 19:14:58 2017 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-# Copyright (c) 2015, University of Kaiserslautern
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Matthias Jung
-
-
-ARCH = ARM
-VARIANT = opt
-#VARIANT = debug
-
-SYSTEMC_INC = /opt/systemc/include
-SYSTEMC_LIB = /opt/systemc/lib-linux64
-
-CXXFLAGS = -I../../build/$(ARCH) -L../../build/$(ARCH)
-CXXFLAGS += -I../systemc/
-CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB)
-CXXFLAGS += -std=c++0x
-CXXFLAGS += -g
-CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DDEBUG -DTRACING_ON
-
-LIBS = -lgem5_$(VARIANT) -lsystemc
-
-ALL = gem5.$(VARIANT).sc
-
-all: $(ALL)
-
-.cc.o:
- $(CXX) $(CXXFLAGS) -c -o $@ $<
-
-sc_gem5_control.o: ../systemc/sc_gem5_control.cc \
- ../systemc/sc_gem5_control.hh
-sc_logger.o: ../systemc/sc_logger.cc ../systemc/sc_logger.hh
-sc_module.o: ../systemc/sc_module.cc ../systemc/sc_module.hh
-sc_mm.o: sc_mm.cc sc_mm.hh
-sc_ext.o: sc_ext.cc sc_ext.hh
-sc_port.o: sc_port.cc sc_port.hh
-sc_target.o: sc_target.cc sc_target.hh
-stats.o: ../systemc/stats.cc ../systemc/stats.hh
-main.o: main.cc ../systemc/sc_logger.hh ../systemc/sc_module.hh \
- ../systemc/stats.hh
-
-gem5.$(VARIANT).sc: main.o ../systemc/stats.o ../systemc/sc_gem5_control.o \
- ../systemc/sc_logger.o ../systemc/sc_module.o sc_mm.o sc_ext.o sc_port.o sc_target.o
- $(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS)
-
-clean:
- $(RM) $(ALL)
- $(RM) *.o
- $(RM) -r m5out
diff -r 594d96c093d0 -r f12963cb9dc2 util/tlm/examples/slave_port/SConstruct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/slave_port/SConstruct Thu Feb 09 19:15:30 2017 -0500
@@ -0,0 +1,77 @@
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+import os
+
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+#gem5_variant = 'debug'
+
+gem5_root = '#../../../..'
+
+target = 'gem5.' + gem5_variant + '.sc'
+
+env = Environment()
+
+# Import PKG_CONFIG_PATH from the external environment
+if os.environ.has_key('PKG_CONFIG_PATH'):
+ env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
+
+# search for SystemC
+env.ParseConfig('pkg-config --cflags --libs systemc')
+
+# add include dirs
+env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
+ gem5_root + '/util/systemc',
+ gem5_root + '/util/tlm'])
+
+env.Append(LIBS=['gem5_' + gem5_variant])
+env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
+
+env.Append(CXXFLAGS=['-std=c++11',
+ '-DSC_INCLUDE_DYNAMIC_PROCESSES',
+ '-DTRACING_ON'])
+
+if gem5_variant == 'debug':
+ env.Append(CXXFLAGS=['-g', '-DDEBUG'])
+
+src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
+ gem5_root + '/util/systemc/sc_logger.cc',
+ gem5_root + '/util/systemc/sc_module.cc',
+ gem5_root + '/util/systemc/stats.cc']
+
+src_tlm = Glob(gem5_root + '/util/tlm/*.cc')
+src_main = Glob('*.cc')
+
+main = env.Program(target, src_systemc + src_tlm + src_main)
diff -r 594d96c093d0 -r f12963cb9dc2 util/tlm/examples/slave_port/main.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/slave_port/main.cc Thu Feb 09 19:15:30 2017 -0500
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ * Christian Menard
+ * Abdul Mutaal Ahmad
+ */
+
+/**
+ * @file
+ *
+ * Example top level file for SystemC-TLM integration with C++-only
+ * instantiation.
+ *
+ */
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_target.hh"
+#include "sim_control.hh"
+#include "stats.hh"
+
+// Defining global string variable decalred in stats.hh
+std::string filename;
+
+void
+reportHandler(const sc_core::sc_report &report,
+ const sc_core::sc_actions &actions)
+{
+ uint64_t systemc_time = report.get_time().value();
+ uint64_t gem5_time = curTick();
+
+ std::cerr << report.get_time();
+
+ if (gem5_time < systemc_time) {
+ std::cerr << " (<) ";
+ } else if (gem5_time > systemc_time) {
+ std::cerr << " (!) ";
+ } else {
+ std::cerr << " (=) ";
+ }
+
+ std::cerr << ": " << report.get_msg_type()
+ << ' ' << report.get_msg() << '\n';
+}
+
+int
+sc_main(int argc, char **argv)
+{
+ sc_core::sc_report_handler::set_handler(reportHandler);
+
+ SimControl sim_control("gem5", argc, argv);
+ Target *memory;
+
+ filename = "m5out/stats-systemc.txt";
+
+ tlm::tlm_initiator_socket <> *mem_port =
+ dynamic_cast<tlm::tlm_initiator_socket<> *>(
+ sc_core::sc_find_object("gem5.memory")
+ );
+
+ if (mem_port) {
+ SC_REPORT_INFO("sc_main", "Port Found");
+ unsigned long long int size = 512*1024*1024ULL;
+ memory = new Target("memory",
+ sim_control.getDebugFlag(),
+ size,
+ sim_control.getOffset());
+
+ memory->socket.bind(*mem_port);
+ } else {
+ SC_REPORT_FATAL("sc_main", "Port Not Found");
+ std::exit(EXIT_FAILURE);
+ }
+
+ sc_core::sc_start();
+
+ SC_REPORT_INFO("sc_main", "End of Simulation");
+
+ CxxConfig::statsDump();
+
+ return EXIT_SUCCESS;
+}
diff -r 594d96c093d0 -r f12963cb9dc2 util/tlm/examples/slave_port/run_gem5.sh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/slave_port/run_gem5.sh Thu Feb 09 19:15:30 2017 -0500
@@ -0,0 +1,53 @@
+#!/bin/bash
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
Christian Menard
2017-02-10 17:38:59 UTC
Permalink
changeset bd67524751ee in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bd67524751ee
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Add the Master Port. Add an example application that isslustrates its
* use.

Testing Done: A simple example application consisting of a TLM traffic
generator and a gem5 memory is part of the patch.

Reviewed at http://reviews.gem5.org/r/3528/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/examples/master_port/SConstruct | 77 ++++
util/tlm/examples/master_port/main.cc | 98 +++++
util/tlm/examples/master_port/tlm.py | 75 ++++
util/tlm/examples/master_port/traffic_generator.cc | 154 ++++++++
util/tlm/examples/master_port/traffic_generator.hh | 77 ++++
util/tlm/sc_master_port.cc | 362 +++++++++++++++++++++
util/tlm/sc_master_port.hh | 137 +++++++
util/tlm/sim_control.cc | 2 +
8 files changed, 982 insertions(+), 0 deletions(-)

diffs (truncated from 1027 to 300 lines):

diff -r f12963cb9dc2 -r bd67524751ee util/tlm/examples/master_port/SConstruct
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/master_port/SConstruct Thu Feb 09 19:15:33 2017 -0500
@@ -0,0 +1,77 @@
+#!python
+
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+import os
+
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+#gem5_variant = 'debug'
+
+gem5_root = '#../../../..'
+
+target = 'gem5.' + gem5_variant + '.sc'
+
+env = Environment()
+
+# Import PKG_CONFIG_PATH from the external environment
+if os.environ.has_key('PKG_CONFIG_PATH'):
+ env['ENV']['PKG_CONFIG_PATH'] = os.environ['PKG_CONFIG_PATH']
+
+# search for SystemC
+env.ParseConfig('pkg-config --cflags --libs systemc')
+
+# add include dirs
+env.Append(CPPPATH=[gem5_root + '/build/' + gem5_arch,
+ gem5_root + '/util/systemc',
+ gem5_root + '/util/tlm'])
+
+env.Append(LIBS=['gem5_' + gem5_variant])
+env.Append(LIBPATH=[gem5_root + '/build/' + gem5_arch])
+
+env.Append(CXXFLAGS=['-std=c++11',
+ '-DSC_INCLUDE_DYNAMIC_PROCESSES',
+ '-DTRACING_ON'])
+
+if gem5_variant == 'debug':
+ env.Append(CXXFLAGS=['-g', '-DDEBUG'])
+
+src_systemc = [gem5_root + '/util/systemc/sc_gem5_control.cc',
+ gem5_root + '/util/systemc/sc_logger.cc',
+ gem5_root + '/util/systemc/sc_module.cc',
+ gem5_root + '/util/systemc/stats.cc']
+
+src_tlm = Glob(gem5_root + '/util/tlm/*.cc')
+src_main = Glob('*.cc')
+
+main = env.Program(target, src_systemc + src_tlm + src_main)
diff -r f12963cb9dc2 -r bd67524751ee util/tlm/examples/master_port/main.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/master_port/main.cc Thu Feb 09 19:15:33 2017 -0500
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_master_port.hh"
+#include "sim_control.hh"
+#include "stats.hh"
+#include "traffic_generator.hh"
+
+// Defining global string variable decalred in stats.hh
+std::string filename;
+
+void
+reportHandler(const sc_core::sc_report& report,
+ const sc_core::sc_actions& actions)
+{
+ uint64_t systemc_time = report.get_time().value();
+ uint64_t gem5_time = curTick();
+
+ std::cerr << report.get_time();
+
+ if (gem5_time < systemc_time) {
+ std::cerr << " (<) ";
+ } else if (gem5_time > systemc_time) {
+ std::cerr << " (!) ";
+ } else {
+ std::cerr << " (=) ";
+ }
+
+ std::cerr << ": " << report.get_msg_type() << ' ' << report.get_msg()
+ << '\n';
+}
+
+int
+sc_main(int argc, char** argv)
+{
+ sc_core::sc_report_handler::set_handler(reportHandler);
+
+ SimControl simControl("gem5", argc, argv);
+ TrafficGenerator trafficGenerator("traffic_generator");
+
+ filename = "m5out/stats-systemc.txt";
+
+ tlm::tlm_target_socket<>* mem_port =
+ dynamic_cast<tlm::tlm_target_socket<>*>(
+ sc_core::sc_find_object("gem5.memory"));
+
+ if (mem_port) {
+ SC_REPORT_INFO("sc_main", "Port Found");
+ trafficGenerator.socket.bind(*mem_port);
+ } else {
+ SC_REPORT_FATAL("sc_main", "Port Not Found");
+ std::exit(EXIT_FAILURE);
+ }
+
+ std::cout << "Starting sc_main" << std::endl;
+
+ sc_core::sc_start(); // Run to end of simulation
+
+ SC_REPORT_INFO("sc_main", "End of Simulation");
+
+ CxxConfig::statsDump();
+
+ return EXIT_SUCCESS;
+}
diff -r f12963cb9dc2 -r bd67524751ee util/tlm/examples/master_port/tlm.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/master_port/tlm.py Thu Feb 09 19:15:33 2017 -0500
@@ -0,0 +1,75 @@
+#
+# Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+#
+
+import m5
+from m5.objects import *
+
+import os
+
+# Base System Architecture:
+# +-----+ ^
+# | TLM | | TLM World
+# +--+--+ | (see main.cc)
+# | v
+# +----------v-----------+ External Port (see sc_master_port.*)
+# | Membus | ^
+# +----------+-----------+ |
+# | | gem5 World
+# +---v----+ |
+# | Memory | |
+# +--------+ v
+#
+
+# Create a system with a Crossbar and a simple Memory:
+system = System()
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory(range = AddrRange('512MB'))
+system.clk_domain = SrcClockDomain(clock = '1.5GHz',
+ voltage_domain = VoltageDomain(voltage = '1V'))
+
+# Create a external TLM port:
+system.tlm = ExternalMaster()
+system.tlm.port_type = "tlm_master"
+system.tlm.port_data = "memory"
+
+# Route the connections:
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
+system.tlm.port = system.membus.slave
+system.mem_mode = 'timing'
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+m5.instantiate()
+m5.simulate()
diff -r f12963cb9dc2 -r bd67524751ee util/tlm/examples/master_port/traffic_generator.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/master_port/traffic_generator.cc Thu Feb 09 19:15:33 2017 -0500
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
Christian Menard
2017-02-10 17:38:59 UTC
Permalink
changeset 3de6ee321c3e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3de6ee321c3e
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Simplify the Slave Port by using a simple_initiator_socket.

Testing Done: Example applications are still running.

Reviewed at http://reviews.gem5.org/r/3686/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/sc_slave_port.cc | 18 +++++-------------
util/tlm/sc_slave_port.hh | 9 ++-------
2 files changed, 7 insertions(+), 20 deletions(-)

diffs (85 lines):

diff -r bd67524751ee -r 3de6ee321c3e util/tlm/sc_slave_port.cc
--- a/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:33 2017 -0500
+++ b/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:35 2017 -0500
@@ -262,7 +262,7 @@
/* Did another request arrive while blocked, schedule a retry */
if (needToSendRequestRetry) {
needToSendRequestRetry = false;
- iSocket.sendRetryReq();
+ sendRetryReq();
}
}
else if (phase == tlm::BEGIN_RESP)
@@ -276,7 +276,7 @@
bool need_retry;
if (packet->needsResponse()) {
packet->makeResponse();
- need_retry = !iSocket.sendTimingResp(packet);
+ need_retry = !sendTimingResp(packet);
} else {
need_retry = false;
}
@@ -311,7 +311,7 @@
blockingResponse = NULL;
PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();

- bool need_retry = !iSocket.sendTimingResp(packet);
+ bool need_retry = !sendTimingResp(packet);

sc_assert(!need_retry);

@@ -333,24 +333,16 @@
return tlm::TLM_ACCEPTED;
}

-void
-SCSlavePort::invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
- sc_dt::uint64 end_range)
-{
- SC_REPORT_FATAL("SCSlavePort", "unimpl. func: invalidate_direct_mem_ptr");
-}
-
SCSlavePort::SCSlavePort(const std::string &name_,
const std::string &systemc_name,
ExternalSlave &owner_) :
- tlm::tlm_initiator_socket<>(systemc_name.c_str()),
ExternalSlave::Port(name_, owner_),
- iSocket(*this),
+ iSocket(systemc_name.c_str()),
blockingRequest(NULL),
needToSendRequestRetry(false),
blockingResponse(NULL)
{
- m_export.bind(*this);
+ iSocket.register_nb_transport_bw(this, &SCSlavePort::nb_transport_bw);
}

class SlavePortHandler : public ExternalSlave::Handler
diff -r bd67524751ee -r 3de6ee321c3e util/tlm/sc_slave_port.hh
--- a/util/tlm/sc_slave_port.hh Thu Feb 09 19:15:33 2017 -0500
+++ b/util/tlm/sc_slave_port.hh Thu Feb 09 19:15:35 2017 -0500
@@ -67,12 +67,10 @@
* original packet as a payload extension, the packet can be restored and send
* back to the gem5 world upon receiving a response from the SystemC world.
*/
-class SCSlavePort : public tlm::tlm_initiator_socket<>,
- public tlm::tlm_bw_transport_if<>,
- public ExternalSlave::Port
+class SCSlavePort : public ExternalSlave::Port
{
public:
- SCSlavePort &iSocket;
+ tlm_utils::simple_initiator_socket<SCSlavePort> iSocket;

/** One instance of pe and the related callback needed */
//payloadEvent<SCSlavePort> pe;
@@ -111,9 +109,6 @@
tlm::tlm_phase& phase,
sc_core::sc_time& t);

- void invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
- sc_dt::uint64 end_range);
-
public:
SCSlavePort(const std::string &name_,
const std::string &systemc_name,
Christian Menard
2017-02-10 17:38:59 UTC
Permalink
changeset 39b0a51c9e76 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=39b0a51c9e76
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Move common code of the example to a common directory. Move the cli
* parsing from the SimControl module to a separate example object. Add
* comments describing the Gem5SimControl module.

Testing Done: Examples compile and run.

Reviewed at http://reviews.gem5.org/r/3695/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/examples/common/cli_parser.cc | 126 +++++++++++++++++++++++++++
util/tlm/examples/common/cli_parser.hh | 70 +++++++++++++++
util/tlm/examples/common/report_handler.cc | 87 ++++++++++++++++++
util/tlm/examples/common/report_handler.hh | 42 +++++++++
util/tlm/examples/master_port/SConstruct | 5 +-
util/tlm/examples/master_port/main.cc | 39 ++------
util/tlm/examples/slave_port/SConstruct | 5 +-
util/tlm/examples/slave_port/main.cc | 47 +++------
util/tlm/sim_control.cc | 134 ++++++++--------------------
util/tlm/sim_control.hh | 48 +++++++--
10 files changed, 431 insertions(+), 172 deletions(-)

diffs (truncated from 796 to 300 lines):

diff -r 3de6ee321c3e -r 39b0a51c9e76 util/tlm/examples/common/cli_parser.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/common/cli_parser.cc Thu Feb 09 19:15:38 2017 -0500
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include <iostream>
+#include <sstream>
+
+#include "cli_parser.hh"
+#include "sim/cxx_manager.hh"
+
+void
+CliParser::usage(const std::string& prog_name)
+{
+ std::cerr
+ << "Usage: " << prog_name
+ << (" <config_file.ini> [ <option> ]\n\n"
+ "OPTIONS:\n"
+
+ " -o <offset> -- set memory offset\n"
+ " -d <flag> -- set a gem5 debug flag\n"
+ " (-<flag> clears a flag)\n"
+ " -v -- verbose output\n"
+ " -e <ticks> -- end of simulation after a \n"
+ " given number of ticks\n"
+ "\n");
+ std::exit(EXIT_FAILURE);
+}
+
+void
+CliParser::parse(int argc, char** argv)
+{
+ std::string prog_name(argv[0]);
+
+ unsigned int arg_ptr = 1;
+
+ if (argc == 1) {
+ usage(prog_name);
+ }
+
+ configFile = std::string(argv[arg_ptr]);
+ arg_ptr++;
+
+ // default values
+ verboseFlag = false;
+ simulationEnd = 0;
+ memoryOffset = 0;
+
+ try {
+ while (arg_ptr < argc) {
+ std::string option(argv[arg_ptr]);
+ arg_ptr++;
+ unsigned num_args = argc - arg_ptr;
+
+ if (option == "-d") {
+ if (num_args < 1) {
+ usage(prog_name);
+ }
+ std::string flag(argv[arg_ptr]);
+ arg_ptr++;
+ debugFlags.push_back(flag);
+ } else if (option == "-e") {
+ if (num_args < 1) {
+ usage(prog_name);
+ }
+ std::istringstream(argv[arg_ptr]) >> simulationEnd;
+ arg_ptr++;
+ } else if (option == "-v") {
+ verboseFlag = true;
+ } else if (option == "-o") {
+ if (num_args < 1) {
+ usage(prog_name);
+ }
+ std::istringstream(argv[arg_ptr]) >> memoryOffset;
+ arg_ptr++;
+ /* code */
+ } else {
+ usage(prog_name);
+ }
+ }
+ } catch (CxxConfigManager::Exception &e) {
+ std::cerr << e.name << ": " << e.message << "\n";
+ std::exit(EXIT_FAILURE);
+ }
+
+ parsed = true;
+}
+
+std::string
+CliParser::getDebugFlags()
+{
+ std::stringstream ss;
+ for (auto& flag : debugFlags) {
+ ss << flag << ' ';
+ }
+ return ss.str();
+}
diff -r 3de6ee321c3e -r 39b0a51c9e76 util/tlm/examples/common/cli_parser.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/common/cli_parser.hh Thu Feb 09 19:15:38 2017 -0500
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __CLI_PARSER_HH__
+#define __CLI_PARSER_HH__
+
+#include <cassert>
+#include <string>
+#include <vector>
+
+class CliParser
+{
+ private:
+ int argc;
+ char** argv;
+
+ bool parsed;
+
+ uint64_t memoryOffset;
+ uint64_t simulationEnd;
+ bool verboseFlag;
+ std::vector<std::string> debugFlags;
+ std::string configFile;
+
+ void usage(const std::string& prog_name);
+ public:
+
+ CliParser() : parsed(false) {}
+
+ void parse(int argc, char** argv);
+
+ uint64_t getMemoryOffset() { assert(parsed); return memoryOffset; }
+ uint64_t getSimulationEnd() { assert(parsed); return simulationEnd; }
+ bool getVerboseFlag() { assert(parsed); return verboseFlag; }
+ std::string getConfigFile() { assert(parsed); return configFile; }
+ std::string getDebugFlags();
+};
+
+#endif
diff -r 3de6ee321c3e -r 39b0a51c9e76 util/tlm/examples/common/report_handler.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/common/report_handler.cc Thu Feb 09 19:15:38 2017 -0500
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include <iostream>
+#include <systemc>
+
+#include <sim/core.hh>
+#include <sim/simulate.hh>
+
+#include "report_handler.hh"
+
+using namespace sc_core;
+
+void
+reportHandler(const sc_report &report, const sc_actions &actions)
+{
+ uint64_t systemc_time = report.get_time().value();
+ uint64_t gem5_time = curTick();
+
+ if (actions & SC_DO_NOTHING)
+ return;
+
+ if (actions & SC_DISPLAY || actions & SC_LOG)
+ {
+ std::ostream& stream = actions & SC_DISPLAY ? std::cout : std::cerr;
+
+ stream << report.get_time();
+
+ if (gem5_time < systemc_time) {
+ stream << " (<) ";
+ } else if (gem5_time > systemc_time) {
+ stream << " (!) ";
+ } else {
+ stream << " (=) ";
+ }
+
+ stream << ": " << report.get_msg_type()
+ << ' ' << report.get_msg() << '\n';
+ }
+
+ if (actions & SC_THROW) {
+ std::cerr << "warning: the report handler ignored a SC_THROW action\n";
+ } else if (actions & SC_INTERRUPT) {
+ std::cerr << "warning: the report handler ignored a SC_INTERRUPT"
+ << "action\n";
+ } else if (actions & SC_CACHE_REPORT) {
+ std::cerr << "warning: the report handler ignored a SC_CACHE_REPORT"
+ << "action\n";
+ }
+
+ if (actions & SC_STOP)
+ sc_stop();
+
+ if (actions & SC_ABORT)
+ abort();
+}
diff -r 3de6ee321c3e -r 39b0a51c9e76 util/tlm/examples/common/report_handler.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/examples/common/report_handler.hh Thu Feb 09 19:15:38 2017 -0500
@@ -0,0 +1,42 @@
+/*
Christian Menard
2017-02-10 17:39:00 UTC
Permalink
changeset 9018cadf6c87 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9018cadf6c87
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.

Reviewed at http://reviews.gem5.org/r/3775/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/examples/master_port/main.cc | 24 +++-------
util/tlm/examples/master_port/tlm.py | 2 +-
util/tlm/examples/slave_port/main.cc | 27 ++++--------
util/tlm/examples/slave_port/run_gem5.sh | 2 +-
util/tlm/examples/slave_port/tlm.py | 2 +-
util/tlm/master_transactor.cc | 62 ++++++++++++++++++++++++++++
util/tlm/master_transactor.hh | 70 ++++++++++++++++++++++++++++++++
util/tlm/sc_master_port.cc | 61 ++++++++++++++-------------
util/tlm/sc_master_port.hh | 32 ++++++++++---
util/tlm/sc_slave_port.cc | 55 ++++++++++++------------
util/tlm/sc_slave_port.hh | 30 ++++++++++---
util/tlm/sim_control.cc | 53 ++++++++++++++++++++++-
util/tlm/sim_control.hh | 17 ++++++-
util/tlm/sim_control_if.hh | 56 +++++++++++++++++++++++++
util/tlm/slave_transactor.cc | 62 ++++++++++++++++++++++++++++
util/tlm/slave_transactor.hh | 70 ++++++++++++++++++++++++++++++++
16 files changed, 510 insertions(+), 115 deletions(-)

diffs (truncated from 1003 to 300 lines):

diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/master_port/main.cc
--- a/util/tlm/examples/master_port/main.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/master_port/main.cc Thu Feb 09 19:15:41 2017 -0500
@@ -36,8 +36,8 @@
#include <tlm>

#include "cli_parser.hh"
+#include "master_transactor.hh"
#include "report_handler.hh"
-#include "sc_master_port.hh"
#include "sim_control.hh"
#include "stats.hh"
#include "traffic_generator.hh"
@@ -50,24 +50,16 @@

sc_core::sc_report_handler::set_handler(reportHandler);

- Gem5SystemC::Gem5SimControl simControl("gem5",
- parser.getConfigFile(),
- parser.getSimulationEnd(),
- parser.getDebugFlags());
+ Gem5SystemC::Gem5SimControl sim_control("gem5",
+ parser.getConfigFile(),
+ parser.getSimulationEnd(),
+ parser.getDebugFlags());

TrafficGenerator trafficGenerator("traffic_generator");
+ Gem5SystemC::Gem5MasterTransactor transactor("transactor", "transactor");

- tlm::tlm_target_socket<>* mem_port =
- dynamic_cast<tlm::tlm_target_socket<>*>(
- sc_core::sc_find_object("gem5.memory"));
-
- if (mem_port) {
- SC_REPORT_INFO("sc_main", "Port Found");
- trafficGenerator.socket.bind(*mem_port);
- } else {
- SC_REPORT_FATAL("sc_main", "Port Not Found");
- std::exit(EXIT_FAILURE);
- }
+ trafficGenerator.socket.bind(transactor.socket);
+ transactor.sim_control.bind(sim_control);

SC_REPORT_INFO("sc_main", "Start of Simulation");

diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/master_port/tlm.py
--- a/util/tlm/examples/master_port/tlm.py Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/master_port/tlm.py Thu Feb 09 19:15:41 2017 -0500
@@ -61,7 +61,7 @@
# Create a external TLM port:
system.tlm = ExternalMaster()
system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"

# Route the connections:
system.system_port = system.membus.slave
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/main.cc
--- a/util/tlm/examples/slave_port/main.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/main.cc Thu Feb 09 19:15:41 2017 -0500
@@ -50,6 +50,7 @@
#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
+#include "slave_transactor.hh"
#include "stats.hh"

int
@@ -60,31 +61,21 @@

sc_core::sc_report_handler::set_handler(reportHandler);

- Gem5SystemC::Gem5SimControl simControl("gem5",
+ Gem5SystemC::Gem5SimControl sim_control("gem5",
parser.getConfigFile(),
parser.getSimulationEnd(),
parser.getDebugFlags());
- Target *memory;

unsigned long long int memorySize = 512*1024*1024ULL;

- tlm::tlm_initiator_socket <> *mem_port =
- dynamic_cast<tlm::tlm_initiator_socket<> *>(
- sc_core::sc_find_object("gem5.memory")
- );
+ Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
+ Target memory("memory",
+ parser.getVerboseFlag(),
+ memorySize,
+ parser.getMemoryOffset());

- if (mem_port) {
- SC_REPORT_INFO("sc_main", "Port Found");
- memory = new Target("memory",
- parser.getVerboseFlag(),
- memorySize,
- parser.getMemoryOffset());
-
- memory->socket.bind(*mem_port);
- } else {
- SC_REPORT_FATAL("sc_main", "Port Not Found");
- std::exit(EXIT_FAILURE);
- }
+ memory.socket.bind(transactor.socket);
+ transactor.sim_control.bind(sim_control);

SC_REPORT_INFO("sc_main", "Start of Simulation");

diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/run_gem5.sh
--- a/util/tlm/examples/slave_port/run_gem5.sh Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/run_gem5.sh Thu Feb 09 19:15:41 2017 -0500
@@ -37,7 +37,7 @@
echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"

../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
---tlm-memory=memory \
+--tlm-memory=transactor \
--cpu-type=timing \
--num-cpu=1 \
--mem-type=SimpleMemory \
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/tlm.py
--- a/util/tlm/examples/slave_port/tlm.py Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/tlm.py Thu Feb 09 19:15:41 2017 -0500
@@ -64,7 +64,7 @@
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('512MB')]
system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"

# Route the connections:
system.cpu.port = system.membus.slave
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/master_transactor.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/master_transactor.cc Thu Feb 09 19:15:41 2017 -0500
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include "master_transactor.hh"
+#include "sc_master_port.hh"
+#include "sim_control.hh"
+
+namespace Gem5SystemC
+{
+
+Gem5MasterTransactor::Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName)
+ : sc_core::sc_module(name),
+ socket(portName.c_str()),
+ sim_control("sim_control"),
+ portName(portName)
+{
+ if (portName.empty()) {
+ SC_REPORT_ERROR(name, "No port name specified!\n");
+ }
+}
+
+void
+Gem5MasterTransactor::before_end_of_elaboration()
+{
+ auto* port = sim_control->getMasterPort(portName);
+
+ port->bindToTransactor(this);
+}
+
+}
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/master_transactor.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/master_transactor.hh Thu Feb 09 19:15:41 2017 -0500
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __GEM5_MASTER_TRANSACTOR_HH__
+#define __GEM5_MASTER_TRANSACTOR_HH__
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_master_port.hh"
+#include "sim_control_if.hh"
+
+namespace Gem5SystemC
+{
+
+class Gem5MasterTransactor : public sc_core::sc_module
+{
+ public:
+ // module interface
+ tlm_utils::simple_target_socket<SCMasterPort> socket;
+ sc_core::sc_port<Gem5SimControlInterface> sim_control;
+
+ private:
+ std::string portName;
+
+ public:
+ SC_HAS_PROCESS(Gem5MasterTransactor);
+
+ Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName);
+
+ void before_end_of_elaboration();
+};
+
+}
+
+#endif
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/sc_master_port.cc
--- a/util/tlm/sc_master_port.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/sc_master_port.cc Thu Feb 09 19:15:41 2017 -0500
@@ -34,6 +34,7 @@

#include <sstream>

+#include "master_transactor.hh"
#include "params/ExternalMaster.hh"
#include "sc_master_port.hh"
#include "sim/system.hh"
@@ -81,18 +82,26 @@
SCMasterPort::SCMasterPort(const std::string& name_,
const std::string& systemc_name,
ExternalMaster& owner_,
- Module& module)
+ Gem5SimControl& simControl)
: ExternalMaster::Port(name_, owner_),
- tSocket(systemc_name.c_str()),
peq(this, &SCMasterPort::peq_cb),
waitForRetry(false),
pendingRequest(nullptr),
needToSendRetry(false),
responseInProgress(false),
- module(module)
+ transactor(nullptr),
+ simControl(simControl)
{
Christian Menard
2017-02-10 17:39:00 UTC
Permalink
changeset 77ab27b06d62 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=77ab27b06d62
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Implement 'pipe through' for gem5 Packets (see explanation below)

Basically, this patch ensures that all transactions that originated in the
gem5 world are converted back to the original packet when entering the gem5
world. So far, this only worked for packets that are responded to by a
SyctemC component (e.g. when a gem5 CPU sends a request to a SystemC
memory). By implementing the 'pipe through' this patch ensures, that
packets that are responded to by a gem5 component (e.g. when a gem5 CPU
sends a request to a gem5 memory via a SystemC interconnect) are handled
properly.

Reviewed at http://reviews.gem5.org/r/3796/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/sc_ext.cc | 1 +
util/tlm/sc_ext.hh | 4 ++
util/tlm/sc_master_port.cc | 88 ++++++++++++++++++++++++++++++++++++++-------
util/tlm/sc_master_port.hh | 8 ++++
util/tlm/sc_slave_port.cc | 22 +++++++---
5 files changed, 101 insertions(+), 22 deletions(-)

diffs (271 lines):

diff -r 9018cadf6c87 -r 77ab27b06d62 util/tlm/sc_ext.cc
--- a/util/tlm/sc_ext.cc Thu Feb 09 19:15:41 2017 -0500
+++ b/util/tlm/sc_ext.cc Thu Feb 09 19:15:43 2017 -0500
@@ -45,6 +45,7 @@
Gem5Extension::Gem5Extension(PacketPtr packet)
{
Packet = packet;
+ pipeThrough = false;
}

Gem5Extension& Gem5Extension::getExtension(const tlm_generic_payload *payload)
diff -r 9018cadf6c87 -r 77ab27b06d62 util/tlm/sc_ext.hh
--- a/util/tlm/sc_ext.hh Thu Feb 09 19:15:41 2017 -0500
+++ b/util/tlm/sc_ext.hh Thu Feb 09 19:15:43 2017 -0500
@@ -62,8 +62,12 @@
getExtension(const tlm::tlm_generic_payload &payload);
PacketPtr getPacket();

+ bool isPipeThrough() const { return pipeThrough; }
+ void setPipeThrough() { pipeThrough = true; }
+
private:
PacketPtr Packet;
+ bool pipeThrough;
};

}
diff -r 9018cadf6c87 -r 77ab27b06d62 util/tlm/sc_master_port.cc
--- a/util/tlm/sc_master_port.cc Thu Feb 09 19:15:41 2017 -0500
+++ b/util/tlm/sc_master_port.cc Thu Feb 09 19:15:43 2017 -0500
@@ -36,6 +36,7 @@

#include "master_transactor.hh"
#include "params/ExternalMaster.hh"
+#include "sc_ext.hh"
#include "sc_master_port.hh"
#include "sim/system.hh"

@@ -87,6 +88,7 @@
peq(this, &SCMasterPort::peq_cb),
waitForRetry(false),
pendingRequest(nullptr),
+ pendingPacket(nullptr),
needToSendRetry(false),
responseInProgress(false),
transactor(nullptr),
@@ -158,6 +160,7 @@
}

// ... and queue the valid transaction
+ trans.acquire();
peq.notify(trans, phase, delay);
return tlm::TLM_ACCEPTED;
}
@@ -191,18 +194,35 @@
{
sc_assert(!waitForRetry);
sc_assert(pendingRequest == nullptr);
+ sc_assert(pendingPacket == nullptr);

trans.acquire();
- auto pkt = generatePacket(trans);
+
+ PacketPtr pkt = nullptr;
+
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet. Otherwise, we
+ // generate a new packet based on the transaction.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ pkt = extension->getPacket();
+ } else {
+ pkt = generatePacket(trans);
+ }

auto tlmSenderState = new TlmSenderState(trans);
pkt->pushSenderState(tlmSenderState);

if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
sendEndReq(trans);
+ trans.release();
} else { // port is blocked -> wait for retry before sending END_REQ
waitForRetry = true;
pendingRequest = &trans;
+ pendingPacket = pkt;
}
}

@@ -236,11 +256,25 @@
SCMasterPort::b_transport(tlm::tlm_generic_payload& trans,
sc_core::sc_time& t)
{
- auto pkt = generatePacket(trans);
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
+ PacketPtr pkt = nullptr;
+
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ pkt = extension->getPacket();
+ } else {
+ pkt = generatePacket(trans);
+ }
+
+ Tick ticks = sendAtomic(pkt);

// send an atomic request to gem5
- Tick ticks = sendAtomic(pkt);
- panic_if(!pkt->isResponse(), "Packet sending failed!\n");
+ panic_if(pkt->needsResponse() && !pkt->isResponse(),
+ "Packet sending failed!\n");

// one tick is a pico second
auto delay =
@@ -249,7 +283,8 @@
// update time
t += delay;

- destroyPacket(pkt);
+ if (extension != nullptr)
+ destroyPacket(pkt);

trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
@@ -257,11 +292,19 @@
unsigned int
SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans)
{
- auto pkt = generatePacket(trans);
+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);

- sendFunctional(pkt);
-
- destroyPacket(pkt);
+ // If there is an extension, this transaction was initiated by the gem5
+ // world and we can pipe through the original packet.
+ if (extension != nullptr) {
+ extension->setPipeThrough();
+ sendFunctional(extension->getPacket());
+ } else {
+ auto pkt = generatePacket(trans);
+ sendFunctional(pkt);
+ destroyPacket(pkt);
+ }

return trans.get_data_length();
}
@@ -291,11 +334,22 @@
sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay);

auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
+ sc_assert(tlmSenderState != nullptr);
+
auto& trans = tlmSenderState->trans;

+ Gem5Extension* extension = nullptr;
+ trans.get_extension(extension);
+
// clean up
delete tlmSenderState;
- destroyPacket(pkt);
+
+ // If there is an extension the packet was piped through and we must not
+ // delete it. The packet travels back with the transaction.
+ if (extension == nullptr)
+ destroyPacket(pkt);
+ else
+ sc_assert(extension->isPipeThrough());

sendBeginResp(trans, delay);
trans.release();
@@ -330,14 +384,18 @@
{
sc_assert(waitForRetry);
sc_assert(pendingRequest != nullptr);
+ sc_assert(pendingPacket != nullptr);

- auto& trans = *pendingRequest;
+ if (sendTimingReq(pendingPacket)) {
+ waitForRetry = false;
+ pendingPacket = nullptr;

- waitForRetry = false;
- pendingRequest = nullptr;
+ auto& trans = *pendingRequest;
+ sendEndReq(trans);
+ trans.release();

- // retry
- handleBeginReq(trans);
+ pendingRequest = nullptr;
+ }
}

void
diff -r 9018cadf6c87 -r 77ab27b06d62 util/tlm/sc_master_port.hh
--- a/util/tlm/sc_master_port.hh Thu Feb 09 19:15:41 2017 -0500
+++ b/util/tlm/sc_master_port.hh Thu Feb 09 19:15:43 2017 -0500
@@ -59,6 +59,13 @@
* added as a sender state to the gem5 packet. This way the payload can be
* restored when the response packet arrives at the port.
*
+ * Special care is required, when the TLM transaction originates from a
+ * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
+ * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
+ * interconnect. In this case, the master port restores the original packet
+ * from the payload extension (added by the SCSlavePort) and forwards it to the
+ * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
+ *
* If gem5 operates in atomic mode, the master port registers the TLM blocking
* interface and automatically translates non-blocking requests to blocking.
* If gem5 operates in timing mode, the transactor registers the non-blocking
@@ -82,6 +89,7 @@

bool waitForRetry;
tlm::tlm_generic_payload* pendingRequest;
+ PacketPtr pendingPacket;

bool needToSendRetry;

diff -r 9018cadf6c87 -r 77ab27b06d62 util/tlm/sc_slave_port.cc
--- a/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:41 2017 -0500
+++ b/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:43 2017 -0500
@@ -265,16 +265,26 @@
{
CAUGHT_UP;

- PacketPtr packet = Gem5Extension::getExtension(trans).getPacket();
+ auto& extension = Gem5Extension::getExtension(trans);
+ auto packet = extension.getPacket();

sc_assert(!blockingResponse);

- bool need_retry;
- if (packet->needsResponse()) {
+ bool need_retry = false;
+
+ /*
+ * If the packet was piped through and needs a response, we don't need
+ * to touch the packet and can forward it directly as a response.
+ * Otherwise, we need to make a response and send the transformed
+ * packet.
+ */
+ if (extension.isPipeThrough()) {
+ if (packet->isResponse()) {
+ need_retry = !sendTimingResp(packet);
+ }
+ } else if (packet->needsResponse()) {
packet->makeResponse();
need_retry = !sendTimingResp(packet);
- } else {
- need_retry = false;
}

if (need_retry) {
@@ -289,8 +299,6 @@
trans.release();
}
}
- } else {
- SC_REPORT_FATAL("SCSlavePort", "Invalid protocol phase in pec");
}
delete pe;
}
Christian Menard
2017-02-10 17:39:00 UTC
Permalink
changeset 9487cdff1bc3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9487cdff1bc3
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* bugfix: The BEGIN_RESP also needs to be handled when END_REQ was
* skipped
and '&trans == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.

Reviewed at http://reviews.gem5.org/r/3797/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/sc_slave_port.cc | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)

diffs (12 lines):

diff -r 77ab27b06d62 -r 9487cdff1bc3 util/tlm/sc_slave_port.cc
--- a/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:43 2017 -0500
+++ b/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:46 2017 -0500
@@ -261,7 +261,7 @@
sendRetryReq();
}
}
- else if (phase == tlm::BEGIN_RESP)
+ if (phase == tlm::BEGIN_RESP)
{
CAUGHT_UP;
Christian Menard
2017-02-10 17:39:00 UTC
Permalink
changeset 2a5b4e334f7d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a5b4e334f7d
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Pay for the header delay that the gem5 XBar annotates to packets.

Reviewed at http://reviews.gem5.org/r/3798/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/sc_master_port.cc | 12 +++++++++---
util/tlm/sc_slave_port.cc | 27 ++++++++++++++++++++++++++-
2 files changed, 35 insertions(+), 4 deletions(-)

diffs (61 lines):

diff -r 9487cdff1bc3 -r 2a5b4e334f7d util/tlm/sc_master_port.cc
--- a/util/tlm/sc_master_port.cc Thu Feb 09 19:15:46 2017 -0500
+++ b/util/tlm/sc_master_port.cc Thu Feb 09 19:15:48 2017 -0500
@@ -329,9 +329,15 @@

sc_assert(pkt->isResponse());

- // pay for annotaded transport delays
- auto delay =
- sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay);
+ /*
+ * Pay for annotated transport delays.
+ *
+ * See recvTimingReq in sc_slave_port.cc for a detailed description.
+ */
+ auto delay = sc_core::sc_time::from_value(pkt->payloadDelay);
+ // reset the delays
+ pkt->payloadDelay = 0;
+ pkt->headerDelay = 0;

auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
sc_assert(tlmSenderState != nullptr);
diff -r 9487cdff1bc3 -r 2a5b4e334f7d util/tlm/sc_slave_port.cc
--- a/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:46 2017 -0500
+++ b/util/tlm/sc_slave_port.cc Thu Feb 09 19:15:48 2017 -0500
@@ -214,9 +214,34 @@
Gem5Extension* extension = new Gem5Extension(packet);
trans->set_auto_extension(extension);

+ /*
+ * Pay for annotated transport delays.
+ *
+ * The header delay marks the point in time, when the packet first is seen
+ * by the transactor. This is the point int time, when the transactor needs
+ * to send the BEGIN_REQ to the SystemC world.
+ *
+ * NOTE: We drop the payload delay here. Normally, the receiver would be
+ * responsible for handling the payload delay. In this case, however,
+ * the receiver is a SystemC module and has no notion of the gem5
+ * transport protocol and we cannot simply forward the
+ * payload delay to the receiving module. Instead, we expect the
+ * receiving SystemC module to model the payload delay by deferring
+ * the END_REQ. This could lead to incorrect delays, if the XBar
+ * payload delay is longer than the time the receiver needs to accept
+ * the request (time between BEGIN_REQ and END_REQ).
+ *
+ * TODO: We could detect the case described above by remembering the
+ * payload delay and comparing it to the time between BEGIN_REQ and
+ * END_REQ. Then, a warning should be printed.
+ */
+ auto delay = sc_core::sc_time::from_value(packet->payloadDelay);
+ // reset the delays
+ packet->payloadDelay = 0;
+ packet->headerDelay = 0;
+
/* Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
* Standard Page 507 for a visualisation of the procedure */
- sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
tlm::tlm_phase phase = tlm::BEGIN_REQ;
tlm::tlm_sync_enum status;
status = transactor->socket->nb_transport_fw(*trans, phase, delay);
Christian Menard
2017-02-10 17:39:01 UTC
Permalink
changeset b20a1364e019 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b20a1364e019
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Add callbacks for the Gem5SimControl that are called at before and
* after simulate()

Reviewed at http://reviews.gem5.org/r/3799/

Signed-off-by: Jason Lowe-Power <***@lowepower.com>

diffstat:

util/tlm/sim_control.cc | 6 ++++++
util/tlm/sim_control.hh | 16 ++++++++++++++++
2 files changed, 22 insertions(+), 0 deletions(-)

diffs (49 lines):

diff -r 2a5b4e334f7d -r b20a1364e019 util/tlm/sim_control.cc
--- a/util/tlm/sim_control.cc Thu Feb 09 19:15:48 2017 -0500
+++ b/util/tlm/sim_control.cc Thu Feb 09 19:15:51 2017 -0500
@@ -152,6 +152,9 @@
void
Gem5SimControl::run()
{
+ // notify callback
+ beforeSimulate();
+
GlobalSimLoopExitEvent *exit_event = NULL;

if (simulationEnd == 0) {
@@ -165,6 +168,9 @@

getEventQueue(0)->dump();

+ // notify callback
+ afterSimulate();
+
#if TRY_CLEAN_DELETE
config_manager->deleteObjects();
#endif
diff -r 2a5b4e334f7d -r b20a1364e019 util/tlm/sim_control.hh
--- a/util/tlm/sim_control.hh Thu Feb 09 19:15:48 2017 -0500
+++ b/util/tlm/sim_control.hh Thu Feb 09 19:15:51 2017 -0500
@@ -77,6 +77,22 @@
/// Pointer to a previously created instance.
static Gem5SimControl* instance;

+ /** A callback that is called from the run thread before gem5 simulation is
+ * started.
+ *
+ * A derived class may use this to perform any additional initializations
+ * prior simulation.
+ */
+ virtual void beforeSimulate() {}
+
+ /** A callback that is called from the run thread after gem5 simulation
+ * completed.
+ *
+ * A derived class may use this to perform any additional tasks after gem5
+ * exits. For instance, a derived class could use this to call sc_stop().
+ */
+ virtual void afterSimulate() {}
+
public:
SC_HAS_PROCESS(Gem5SimControl);
Christian Menard
2017-02-13 20:25:50 UTC
Permalink
changeset 4d1f9823013a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4d1f9823013a
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Update the README

diffstat:

util/tlm/README | 174 +++++++++++++++++++++++++++++++++++++++++--------------
1 files changed, 128 insertions(+), 46 deletions(-)

diffs (253 lines):

diff -r 3c38d3e74980 -r 4d1f9823013a util/tlm/README
--- a/util/tlm/README Sun Feb 12 15:00:03 2017 -0500
+++ b/util/tlm/README Mon Feb 13 14:25:16 2017 -0600
@@ -1,17 +1,77 @@
-This directory contains a demo of a coupling between gem5 and SystemC-TLM.
-It is based on the gem5-systemc implementation in utils/systemc.
-First a simple example with gem5's traffic generator is shown, later an full
-system example.
+This directory contains a demo of a coupling between gem5 and SystemC-TLM. It
+is based on the gem5-systemc implementation in utils/systemc. This Readme gives
+an overall overview (I), describes the source files in this directory (II),
+explains the build steps (III), shows how to run example simulations (IV-VI)
+and lists known issues (VII).

-Files:

- main.cc -- demonstration top level
- sc_port.{cc,hh} -- transactor that translates beween gem5 and tlm
- sc_mm.{cc,hh} -- implementation of a tlm memory manager
- sc_ext.{cc,hh} -- a TLM extension that carries the gem5 packet
- sc_target.{cc,hh} -- an example TLM LT/AT memory module
- tlm.py -- simple gem5 configuration
- tgen.cfg -- configuration file for the traceplayer
+I. Overview
+===========
+
+The sources in this directory provide three SystemC modules that manage the
+SystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
+Gem5SlaveTransactor. They also implement gem5's ExternalMaster::Port interface
+(SCMasterPort) and ExternalSlave::Port interface (SCSlavePort).
+
+**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
+bridge. SCMasterPort implements gem5's ExternalMaster::Port interface and forms
+the gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
+provides a target socket and represents the TLM side of the bridge. All TLM
+requests send to this target socket, are translated to gem5 requests and
+forwarded to the gem5 world through the SCMasterPort. Then the gem5 world
+handles the request and eventually issues a response. When the response arrives
+at the SCMasterPort it gets translated back into a TLM response and forwarded
+to the TLM world through target socket of the Gem5MasterTransactor.
+SCMasterPort and Gem5MasterTransactor are bound to each other by configuring
+them for the same port name.
+
+**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge.
+Gem5SlaveTransactor is a SystemC module that provides a initiator socket and
+represents the TLM end of the bridge. SCSlavePort implements gem5's
+ExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
+requests send to the SCSlavePort, are translated to TLM requests and forwarded
+to the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
+the TLM world handles the request and eventually issues a response. When the
+response arrives at the Gem5SlaveTransactor it gets translated back into a TLM
+response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort
+and Gem5SlaveTransactor are bound to each other by configuring them for the
+same port name.
+
+**Gem5SimControl** is the central SystemC module that represents the complete
+gem5 world. It is responsible for instantiating all gem5 objects according to a
+given configuration file, for configuring the simulation and for maintaining
+the gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort
+and responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor
+modules to their gem5 counterparts. This module must be instantiated exactly
+once in order to run a gem5 simulation from within an SystemC environment.
+
+
+II. Files
+=========
+
+ sc_slave_port.{cc,hh} -- Implements SCSlavePort
+ sc_master_port.{cc,hh} -- Implements SCMasterPort
+ sc_mm.{cc,hh} -- Implementation of a TLM memory manager
+ sc_ext.{cc,hh} -- TLM extension that carries a gem5 packet
+ sc_peq.{cc,hh} -- TLM PEQ for scheduling gem5 events
+ sim_control.{cc,hh} -- Implements Gem5SimControl
+ slave_transactor.{cc,hh} -- Implements Gem5SlaveTransactor
+ master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
+
+ example/common/cli_parser.{cc,hh} -- Simple cli argument parser
+ example/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
+
+ example/slave_port/main.cc -- demonstration of the slave port
+ example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
+ example/slave_port/tlm.py -- simple gem5 configuration
+ example/slave_port/tlm_elastic.py -- gem5 configuration with an elastic
+ trace replayer
+ example/slave_port/tgen.cfg -- elastic traceplayer configuration
+
+ example/master_port/main.cc -- demonstration of the master port
+ example/master_port/traffic_generator.{cc/hh}
+ -- an example traffic generator module
+ example/master_port/tlm.py -- simple gem5 configuration

Other Files will be used from utils/systemc example:

@@ -21,10 +81,8 @@
stats.{cc,hh}


-I. Traffic Generator Setup
-==========================
-
-To build:
+III. Build
+==========

First build a normal gem5 (cxx-config not needed, Python needed).
Second build gem5 as a library with cxx-config support and (optionally)
@@ -32,11 +90,13 @@
cd ../..
scons build/ARM/gem5.opt
-> scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
+> scons --with-cxx-config --without-python --without-tcmalloc \
+> build/ARM/libgem5_opt.so
cd util/tlm
Note: For MAC / OSX this command should be used:
-> scons --with-cxx-config --without-python build/ARM/libgem5_opt.dylib
+> scons --with-cxx-config --without-python --without-tcmalloc \
+> build/ARM/libgem5_opt.dylib
export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
@@ -44,29 +104,35 @@
export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
-Then edit the Makefile to set the paths for SystemC:
+The build system finds your SystemC installation using pkg-config. Make sure
+that pkg-config is installed and your systemc.pc is within your
+PKG_CONFIG_PATH. You can add SystemC to the PKG_CONFIG_PATH using the following
+command:
+> export PKG_CONFIG_PATH="/path/to/systemc/lib-<arch>/pkgconfig/:$PKG_CONFIG_PATH"

- Linux:
- SYSTEMC_INC = /opt/systemc/include
- SYSTEMC_LIB = /opt/systemc/lib-linux64
+To build one of the examples:

- MAC / OSX:
- SYSTEMC_INC = /opt/systemc/include
- SYSTEMC_LIB = /opt/systemc/lib-macosx64
+> cd examples/{master,slave}_port
+> scons
+> cd ../../

-Then run make:

-> make
+IV. Simple Examples
+===================

-Make a config file for the C++-configured gem5 using normal gem5
+> cd examples/{master,slave}_port

-> ../../build/ARM/gem5.opt ./tlm.py
+In order to run our example simulation, we first need to create a config.ini
+that represents the gem5 configuration. We do so by starting gem5 with the
+desired python configuration script.

-The message "fatal: Can't find port handler type 'tlm'" is okay.
+> ../../../../build/ARM/gem5.opt ./tlm.py
+
+The message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
The configuration will be stored in the m5out/ directory

-The binary 'gem5.opt.sc', that has been created in the make step,
-can now be used to load in the generated config file from the previous
+The build step creates a binary gem5.opt.sc in the example directory. It can
+now be used to load in the generated configuration file from the previous
normal gem5 run.

Try:
@@ -75,28 +141,35 @@

It should run a simulation for 1us.

-To see more information what happens inside the TLM module use the -D flag:
+To see more information what happens inside the TLM modules use the -v flag:

-> ./gem5.opt.sc m5out/config.ini -e 1000000 -D
+> ./gem5.opt.sc m5out/config.ini -e 1000000 -v
./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
-II. Full System Setup
+
+V. Full System Setup
=====================

-Build gem5 as discribed in Section I. Then, make a config file for the
+Apart from the simple examples, there is a full system example that uses
+the gem5-to-TLM bridge.
+
+>cd examples/slave_port
+
+Build gem5 as described in Section III. Then, make a config file for the
C++-configured gem5 using normal gem5

-> ../../build/ARM/gem5.opt ../../configs/example/fs.py --tlm-memory=memory \
- --cpu-type=timing --num-cpu=1 --mem-type=SimpleMemory --mem-size=512MB \
- --mem-channels=1 --caches --l2cache --machine-type=VExpress_EMM \
- --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
- --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
+> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
+ --tlm-memory=transactor --cpu-type=timing --num-cpu=1 \
+ --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
+ --l2cache --machine-type=VExpress_EMM \
+ --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
+ --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img

-The message "fatal: Can't find port handler type 'tlm'" is okay.
+The message "fatal: Can't find port handler type 'tlm_slave'" is okay.
The configuration will be stored in the m5out/ directory

The binary 'gem5.opt.sc' can now be used to load in the generated config
@@ -109,10 +182,10 @@
The parameter -o specifies the begining of the memory region (0x80000000).
The system should boot now.

-For conveniance a run_gem5.sh file holds all those commands
+For convenience a run_gem5.sh file holds all those commands


-III. Elastic Trace Setup
+VI. Elastic Trace Setup
========================

Elastic traces can also be replayed into the SystemC world.
@@ -126,10 +199,19 @@
IEEE International Conference on Embedded Computer Systems Architectures
Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.

-Similar to I. the simulation can be set up with this command:
+Similar IV. the simulation can be set up with this command:

-> ../../build/ARM/gem5.opt ./tlm_elastic.py
+> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
./gem5.opt.sc m5out/config.ini
+
+
+VII. Knwon issues
+=================
+
+* For some toolchains, compiling libgem5 with tcmalloc leads to errors
+ ('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
+ SystemC application.
+* When SystemC was build with --enable-pthreads, SystemC applications linked
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