[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add getter and setter to CacheBlk::whenReady

[Daniel Carvalho (Gerrit)]

Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14715


Change subject: mem-cache: Add getter and setter to CacheBlk::whenReady
......................................................................

mem-cache: Add getter and setter to CacheBlk::whenReady

Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that accesses to a block follow a
chronological order.

As a side effect, now both tickInserted and whenReady retain their
values until updated, that is, they are not reset in invalidate().

Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <***@yahoo.com.br>
---
M src/mem/cache/base.cc
M src/mem/cache/cache_blk.hh
2 files changed, 43 insertions(+), 15 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 244d7ce..bad24f7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -900,10 +900,11 @@
}

// Check if the block to be accessed is available. If not, apply
the
- // access latency on top of block->whenReady.
- if (blk->whenReady > curTick() &&
- ticksToCycles(blk->whenReady - curTick()) > lat) {
- lat += ticksToCycles(blk->whenReady - curTick());
+ // access latency on top of when the block is ready to be accessed.
+ const Tick when_ready = blk->getWhenReady();
+ if (when_ready > curTick() &&
+ ticksToCycles(when_ready - curTick()) > lat) {
+ lat += ticksToCycles(when_ready - curTick());
}
}

@@ -1024,8 +1025,8 @@
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
// populate the time when the block will be ready to access.
- blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
- pkt->payloadDelay;
+ blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay);
return true;
} else if (pkt->cmd == MemCmd::CleanEvict) {
if (blk) {
@@ -1081,8 +1082,8 @@

incHitCount(pkt);
// populate the time when the block will be ready to access.
- blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
- pkt->payloadDelay;
+ blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay);
// if this a write-through packet it will be sent to cache
// below
return !pkt->writeThrough();
@@ -1212,8 +1213,7 @@
pkt->writeDataToBlock(blk->data, blkSize);
}
// We pay for fillLatency here.
- blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
- pkt->payloadDelay;
+ blk->setWhenReady(clockEdge(fillLatency) + pkt->payloadDelay);

return blk;
}
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index d7530d6..e7c7790 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -105,7 +105,10 @@
/** The current status of this block. @sa CacheBlockStatusBits */
State status;

- /** Which curTick() will this block be accessible */
+ /**
+ * Which curTick() will this block be accessible. Its value is only
+ * meaningful if the block is valid.
+ */
Tick whenReady;

/** Number of references to this block since it was brought in. */
@@ -114,7 +117,10 @@
/** holds the source requestor ID for this block. */
int srcMasterId;

- /** Tick on which the block was inserted in the cache. */
+ /**
+ * Tick on which the block was inserted in the cache. Its value is only
+ * meaningful if the block is valid.
+ */
Tick tickInserted;

protected:
@@ -160,7 +166,7 @@
std::list<Lock> lockList;

public:
- CacheBlk() : data(nullptr)
+ CacheBlk() : data(nullptr), whenReady(0), tickInserted(0)
{
invalidate();
}
@@ -208,10 +214,8 @@
tag = MaxAddr;
task_id = ContextSwitchTaskId::Unknown;
status = 0;
- whenReady = MaxTick;
refCount = 0;
srcMasterId = Request::invldMasterId;
- tickInserted = MaxTick;
lockList.clear();
}

@@ -261,6 +265,30 @@
}

/**
+ * Get tick at which block's data will be available for access.
+ *
+ * @return Data ready tick.
+ */
+ Tick getWhenReady() const
+ {
+ return whenReady;
+ }
+
+ /**
+ * Set tick at which block's data will be available for access. The new
+ * tick must be chronologically sequential with respect to previous
+ * accesses.
+ *
+ * @param New data ready tick.
+ */
+ void setWhenReady(const Tick tick)
+ {
+ assert(tick >= whenReady);
+ assert(tick >= tickInserted);
+ whenReady = tick;
+ }
+
+ /**
* Set member variables when a block insertion occurs. Resets reference
* count to 1 (the insertion counts as a reference), and touch block if
* it hadn't been touched previously. Sets the insertion tick to the
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14715
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Gerrit-Change-Number: 14715
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <***@yahoo.com.br>
Gerrit-MessageType: newchange